AD9250BCPZRL7-250

The AD9250 is a dual-channel 14-bit ADC with a maximum sample rate of 250 MSPS designed to provide a solution for low-cost, small-size, wide-bandwidth, multi-function communication applications.

This ADC core adopts a multi-level, differential pipeline architecture and integrates output error correction logic. The ADC core has a wide bandwidth input and supports a variety of user-selectable input ranges. Integrated voltage reference simplifies design. The duty cycle stabilizer can be used to compensate for fluctuations in the ADC clock duty cycle, allowing the converter to maintain excellent performance. JESD204B high-speed serial interface reduces board routing requirements and reduces the number of pins required for the receiver device.

By default, ADC output data is routed directly to two JESD204B serial output channels, which are set to CML levels. The four modes support any combination of M = 1 or 2 (single or dual channel converter) and L = 1 or 2 (single or dual channel). In dual-channel ADC mode, data can be sent over two channels at a maximum sample rate of 250 MSPS. However, if data is sent over one channel, only sample rates up to 125 MSPS are supported. The devices provide synchronous inputs (SYNCINB± and SYSREF±).

Flexible shutdown options can significantly reduce power consumption when needed. Each channel supports programmable over-range level detection via a dedicated fast detection pin.

Setup and control programming is done using a three-wire SPI-compatible serial interface.

The AD9250 is available in a 48-pin LFCSP package and is rated for the −40°C to +85°C industrial temperature range.

1. 集成双通道、14位、170 MSPS/250 MSPS ADC。
2. 可配置的JESD204B输出模块支持每通道最高5 Gbps的采样速率。
3. 片内锁相环(PLL)允许用户提供单个ADC采样时钟，对应JESD204B数据速率时钟由PLL乘以该ADC采样时钟产生。
4. 支持可选RF时钟输入以简化系统板设计。
5. 取得专利的差分输入在最高至400 MHz的输入频率下仍保持出色的信噪比(SNR)性能。
6. 采用1.8 V单电源供电。
7. 标准串行端口接口(SPI)支持各种产品特性和功能，例如：控制时钟DCS、省电模式、测试模式、基准电压模式、超量程快速检测以及串行输出配置等。