peculiarity
Operates from a single 1.8V supply.
Power adjusts the clock frequency.
Internal sampling and holding.
Internal or external reference.
Power-down mode.
Offset binary or 2 complement output data format.
LVDS or CMOS output signal.
60-pin LLP package (9x9x0.8mm, 0.5-pin pitch)
Clock duty cycle stabilizer.
If the sampling bandwidth > 900MHz.
illustrate
"The ADC10DV200 is a monolithic analog-to-digital converter with the ability to convert two analog input signals to 10-bit numbers at a rate of up to 200 megasamples per second (MSPS). Digital output modes are selectable and can be differential LVDS or CMOS signals. The converter uses digital error correction and a differential pipeline architecture with on-chip sample-and-hold circuitry to minimize mold size and power consumption while providing excellent dynamic performance. A unique sample-and-hold stage yields a full power bandwidth of 900MHz. Manufactured on the core CMOS process, the ADC10DV200 can operate from a single 1.8V supply. The ADC10DV200 achieves approximately 9.6 effective bits in Nyquist and consumes 200MSPS in CMOS mode and 450MW LVDS mode with 200MSPS and 170MSPS 280mW. By reducing the sample rate, the power consumption can be further reduced.
Main specifications
resolution
10 bits
Conversion rate
200 MSPS
ENOB
9.6 bits (typical) at @鱼翅 = 70MHz
Signal-to-noise ratio
59.9 dBFS (typical) @鱼翅 = 70MHz
SINAD
59.9 dBFS (typical) @鱼翅 = 70MHz
Spurious-free dynamic range (SFDR)
82 dBFS (typical) @鱼翅 = 70MHz
Power supply for LVDS
450MW (typical) @ FS = 200MSPS
CMOS power supply
280mW (typical) @ FS = 170MSPS
Operating temperature. range
-40°C to +85°C.
apply
communication
Medical imaging
Portable meter
Digital video