illustrate

The CDCE72010 is a high performance, low phase noise and low skew clock synchronizer that synchronizes one VCXO (voltage controlled crystal oscillator) or VCO (voltage controlled oscillator) frequency with one of two base clocks. The clock path is fully programmable, providing a high degree of flexibility for the user. The following relationship applies to separation:

Frequency (VCXO_IN or AUX_IN) / Frequency (PRI_REF or SEC_REF) = (North of p *) / (male of R *)

The VC(X)O_IN clock runs up to 1.5GHz, through the selection of external venture capital (X) O and loop filtering components. PLL loop bandwidth and damping factors can be adjusted to meet different system requirements.

The CDCE72010 can be locked with two base clock inputs (PRI_REF and SEC_REF) and one support frequency to remain fail-safe and system redundant mode.

characteristic

• High performance LVPECL, LVDS, LVCMOS PLL clock synchronization
• Two reference clock inputs (primary and secondary clocks) are redundant with manual or automatic selection support
• Accepts two differential inputs (LVPECL or LVDS) with a reference up to 500MHz (or two LVCMOS inputs up to 250MHz) as a PLL reference
• VCXO_IN clock is synchronized to one or two base clocks
• VCXO_IN frequencies up to 1.5GHz (LVPECL)
  Road LVCMOS for LVDS 800MHz and 250MHz signal levels
• The output can be a combination of LVPECL, LVDS, and LVCMOS (up to 10 differential LVPECL or LVDS outputs or up to 20 LVCMOS outputs), and output 9 can be converted to a second venture capital (X) with an auxiliary input
• The divider outputs are selectable by dividing by 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 18, 20, 24, 28, 30, 32, 36, 40, 42, 48, 50, 56, 60, 64, 70, or 80 up to eight separate dividers at each output. (Except output 0 and 9, 0 follows output 1, output divider and output 9 follows output 8)
• Controllable device settings for SPI
• Individual control is enabled via the SPI interface output
• Integrated on-chip non-volatile memory (EEPROM) to store settings is not required to apply to high-voltage devices
• An optional configuration pin to select two default settings stored in EEPROM
• High efficiency low jitter PLL loop bandwidth from cleaning
• Very low phase noise at the heart of a phase-locked loop
• Programmable phase offset (reference input and output)
• Wide charge pump current range from 200μA to 3mA
• Dedicated charge pump supply voltage range for tuning VCOs
• The preset charge pump is V_{CC_CP}The /2 fast center frequency is set by the VC(X) OS-BUS SPI by control
• SERDES startup mode (VCXO range)
• Auxiliary inputs: Output 9 can be used as a second VCXO driver for all inputs and outputs, or as a PLL feedback signal
• RESETorHOLDThe input pin acts as a reset or hold function