DS90C383BMT

• There are no special pins that require clock/data and /PD between the boot sequences. The input signals (clock and data) can be used to power the device before or after.
• It supports spread spectrum clock modulation frequency up to 100kHz ± 2.5% and propagation center deviation or -5% downward spread.
• The "Input Clock Detection" function will double pull all LVDS to the logic low input clock when the /PD pin is logic high.
• Shift clock support from 18 to 68 MHz
• The most advanced settings and hold time on TxINPUTs
• 发射功率消耗
• BiCMOS with more than 40% lower power consumption
• 发射省电模式
• Dual Pixel with support for VGA, SVGA, XGA and SXGA.
• Narrow bus cable size and reduced cost
• Up to 1.8 Gbps throughput
• Up to 227 MB/s bandwidth
• 345 mV (typical) LVDS swing device with low electromagnetic interference
• PLLs require no external components
• Compliant with TIA/EIA-644 LVDS standard
• Low-profile 56-pin TSSOP package
• Replacement Improvements: SN75LVDS83, DS90C383A

illustrate

The DS90C383B transmitter converts into 4 CMOS/TTL data bits of the LVDS (Low Voltage Differential Signaling) data stream28. A fifth LVDS link stream is transmitted in parallel with the clock and data. 28 bits of input data are transmitted per clock cycle for sampling and transmission. A 65 MHz clock frequency, 24-bit RGB data and 3 LCD timing and control data (FPLINE, FFFRAME, DRDY bits) are transmitted at a rate of 455 Mbps in an LVDS data channel. It uses a 65 MHz clock and has a data throughput of 227 megabytes per second. The DS90C383B transmitter can be programmed to Rising to strobe or descend edge strobe via a dedicated pin edge. The rising edge or falling edge strobe transmitter will intercommunicate with the falling edge strobe receiver (DS90CF386) without any conversion logic.

This chipset is an ideal means to solve problems related to EMI and TTL interfaces with cable size, width, high rotational speed.