DS92CK16TMTC

• Backplane clock selection in master/slave applications
• 125 MHz operating frequency (typical)
• 100 ps duty cycle distortion (typical)
• 50 ps channel-to-channel deviation (typical)
• 3.3V power supply design
• Trouble-free power supply at the clkI/O pin
• Low power design (20 mA@3.3 V static)
• Accept a small swing (300 mV typical) differential signal level
• Industrial temperature operating range (-40 °C to +85°C)
• 24-pin TSSOP package

illustrate

The 1 to 6 DS92CK16 clock buffer/bus transceiver is a one- to six-month CMOS differential clock distribution device that utilizes the bus's low voltage differential signaling (BLVDS) technology. This clock distribution device is designed for applications requiring ultra-low power, low noise, and high data rates. The BLVDS side is a channel transceiver that acts as a separate return/source clock.

The DS92CK16 accepts LVDS (300 mV typical) differential input levels and converts them to a CMOS output level of 3V. The OE# output enable pin, when high, forces all clocks_outputHigh pins.

The device can be used as a source synchronization drive. The selected drive source is controlled by_middleCrdCLK and DE# pins. The device can be used as a master clock, driving input on other clock I/O pins in a multipoint environment. The choice of master/slave clock is implemented along the backplane.