DS90CR217MTDX

• Shift clock support from 20 to 85 MHz
• Receiver output clock duty cycle 50%
• The best class settings and keep TxINPUTS in the times
• Low power consumption
• ± 1V common-mode range (approximately +1.2 V)
• The narrow bus reduces the size and cost of the cable
• to 1.785 Gbps throughput
• 223 megabytes per second bandwidth
• Low EMI of 345 millivolts (typical) oscillating LVDS devices
• The PLL requires no external components
• Ascending edge data gating
• Compatible with the TIA/EIA-644 LVDS standard
• Low profile 48-pin TSSOP package

illustrate

DS90CR217 transmitter converts 21-bit CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted simultaneously with the fourth LVDS link traffic. Each transmit clock cycle, 21-bit input data is sampled and transmitted. At a transmit clock frequency of 85 MHz, 21-bit TTL data is transmitted at a speed of 595 Mbps per LVDS data channel. Using an 85 MHz clock, the data throughput is 1.785 Gbit/s (223 MB/s).

Narrow bus and LVDS signal DS90CR217 is an ideal solution to EMI and cable size wide, high-speed TTL interface problems.