DS90CR485VS

• Up to 6.384 Gbps throughput
• 66MHz to 133MHz input clock support
• Reduce the size and cost of cables and connectors
• Pre-emphasis reduces the load effect of the cable
• DC balancing reduces ISI distortion
• 24-bit dual-force input
• Fault-tolerant 3V LVCMOS/LVTTL input
• Low power consumption, 2.5V power supply
• Flow through the pinout
• Available in a 100-pin TQFP package
• Complies with TIA/EIA-644-A LVDS standards.

illustrate

The DS90CR485 serializes 24 to 8 low-voltage differential signaling (LVDS) streams to the dual advantage of LVCMOS/LVTTL inputs (48 bits of latched data per clock cycle). The phase-locked transmission clock also exceeds the traffic of the ninth LVDS link in parallel. The wide range of TTL buses is reduced to several LVDS transmission lines, reducing the size and cost of cables and connectors. Rising and falling edge clock strobe on bilateral input data. This minimizes the number of pins required and simplifies chip and serial PCB routing between hosts.

The chip is an ideal solution to solve the size problem of EMI and interconnect points to point high throughput applications.

The DS90CR485 is intended for use with the DS90CR486 channel link receiver. It is also backwards compatible with other channels such as DS90CR482 and DS90CR484 reception.