DS50PCI401SQE
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DS50PCI401SQE

  • Category:Digital ICs
  • Product Name:2.5 Gbps/5.0 Gbps 4-lane PCI Express repeater with equalization and de-emphasis
  • Manufacturers:NSC
  • Production Batch Number:10+
  • Encapsulation:QFN52
  • Stock Status:There is stock
  • Stock Quantity:2000
  • Minimum order quantity: 1
  • Details:Click here to find pdf information on the DS50PCI401SQE
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  • Product introduction

peculiarity

  • PCIe for input and output signal conditioning is achieved by adding backplanes and cables
  • FR4" 5Gbps user interface after 0.09 at 42" in residual deterministic jitter (input EQ)
  • 0.11 UI 7 m 5Gbps PCIe cable residual deterministic jitter (equalization with input)
  • 0.09 UI FR4 up to 5Gbps 28" residual deterministic jitter (output go)
  • 0.13 UI with PCIe cable 7 m 5Gbps residual deterministic jitter (output go)
  • Adjustable VOD 800 to 1200mVp - P
  • Automatic power management via SMBus on an individual lane basis
  • Adjustable electrical idle detection threshold.
  • Data rate optimization with 3 stages of equalization with 26 dB gain
  • Optimized data transmission rate 6 levels, 0 to 12 dB emission de-emphasis
  • Flow-through 10mmx5.5mm leadout, 54-pin leadless LLP package
  • Operates from a single 2.5V supply
  • > 6KV HBM ESD rating
  • -10 to 85 °C operating temperature range

illustrate

The DS50PCI401 is a low-power, 4-lane bidirectional buffer/equalizer designed for PCI Express Gen1 and Gen2 applications. The device performs receive equalization and send de-emphasis, allowing for physical locations within a system for maximum flexibility. The receiver is an open input whose eyes are completely closed due to inter-symbol interference (ISI) caused by the interconnect medium.

The transmitter can be de-emphasized by the user based on the distance from the PCI Express endpoint of the DS50PCI401. The DS50PCI401 contains PCI Express-specific functions such as transmit idle receive detection and beacon signal pass.

The device will change the load impedance based on the input pin RXDETA/B input status detection. An internal rate of return detection circuit consists of detecting if the incoming data stream is in the second generation of the data transfer rate, and adjusting its output accordingly to de-emphasize. Signal conditioning is provided by the devices so that the system upgrades without reducing the data transfer rate of their body to reach from the first generation to the second generation. This is true FR4 applications, such as backplanes, as well as cable interconnects.

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