DS99R101VS

• 3 MHz 40 MHz clock embedded and DC balanced 24:1 and 1:24 data transmission
• User-selectable clock edge transmitter and receive parallel data
• Internal DC-balanced encoding/decoding - Supports an AC-coupled interface without external coding
• Personal power-down control transmitter and reception
• CDR (clock and data recovery) of embedded clocks is received and no external source of reference clock is required
• All code RDL (Random Data Lock) to support field-pluggable applications
• The LOCK output flag is flagged to ensure data integrity at the receiving end
• Balance T_SETUP/t between receivers_HeldRCLK and RDATA
• PTO (step-on) LVCMOS output to reduce EMI and minimize the effects of SSO
• All LVCMOS input and control pins are internally pulled down
• Filters on the transmitter and receiver PLL chips
• 48-pin TQFP package
• Pure CMOS 0.35 micron process
• Supply voltage range: 3.3V ± 10%
• Temperature range 0 °C to +70 °C
• 8 kV HBM ESD tolerance

illustrate

The DS99R101/DS99R102 chipsets convert the 24-bit parallel bus into a fully transparent data/control LVDS serial data stream with embedded clock information. This single serial data stream simplifies the transmission of PCB traces and cables by eliminating skew issues between parallel data and clock paths, and transporting 24-bit buses. It saves system cost and shrinks the data path, which reduces the PCB layers, cable width, and connector size and pins.

The DS99R101/DS99R102 use LVDS high-speed I/O signals LVDS provides a low-power and low-noise environment for reliably transmitting data through the serial transmission path. By optimizing the serializer output edge rate, EMI over the operating frequency range is further reduced.

Internal DC-balanced encoding/decoding is used to support AC-coupled interconnects.