DS99R102VS

• 3 MHz-40 MHz clock two four 1 DC-Balancing bridge embedding and data transmission
• The user selects the clock edge to go parallel to the data of both transmitters and receivers
• Encode/Decode Internal DC Balancing – Supports AC-coupling interface with no external encoding requirements
• Personal power-down control is controlled on both transmitters and receivers
• Embedded clock CDR (Clock and Data Recovery) in the receiver, no external source of reference clock is required
• All of this code RDL (Random Data Lock) supports live-pluggable applications
• Lock to ensure data integrity, output the flag on one side of the receiver
• Balance T_{Set up} / T_Hold RCLK RDATA, on the receiver side
• PTO (Progressive Stimulus) LVCMOS output reduces EMI and reduces the impact of ship security guards (SSOs).
• All inputs and LVCMOS pins are internally controlled to pull down
• Filters PLLs kanji transmitters and receivers
• 48-pin TQFP packaging
• Pure CMOS. 35 μm process
• Supply range: 3.3 V±10%
• 0°C temperature range + 70°C
• 8 kV constant ESD tolerance

description

The DS99R101/DS99R102 chipsets translate the 24-bit reduced parallel bus into a fully transparent data/control serial LVDS stream embedded clock information. This single serial stream transfer 24-bit reduced bus simplifies PCB wires and cables by eliminating the problem of deviation between parallel data and clock paths. This saves system cost data paths, reduces PCB layers, cable width, number of connectors, and pins in turn.

DS99R101/DS99R102 sets LVDS signals in high-speed I/O. LVDS provides a low power and low noise environment for a reliable transmission path over a serial data transmission. Electromagnetic interference (EMI) is further reduced by optimizing the serializer output edge rate to operate over the frequency range.

An internal DC-balanced encoding/decoding is used to support AC-Coupled connections.