TMS320DM642AZDK
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TMS320DM642AZDK

  • Category:processor
  • Product Name:High-performance digital media processor
  • Manufacturers:TI
  • Production Batch Number:10+
  • Encapsulation:BGA
  • Stock Status:There is stock
  • Stock Quantity:500
  • Minimum order quantity: 1
  • Details:Click here to find pdf information on the TMS320DM642AZDK
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  • Product introduction

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This company has stock processing, if there is a real demand, please contact the sales staff and we will do what you accept.

 

 

The TMS320C64x™DSP (including the TMS320DM642 appliance) is the highest performance fixed-point DSP generation on the TMS320C6000™DSP platform. The TMS320DM642 (DM642) device is based on the second generation of high-performance, advanced VelociTI Very Long Instruction Word (VLIW) architecture (VelociTI.2™™) developed by Texas Instruments, making these DSPs an excellent first choice for digital media applications. The C64x™ is a member of the C6000™DSP platform code compatible.

With a clock rate of 720 MHz and millions of instructions per second (MIPS) performance, the DM642 device provides a cost-effective solution to the programming challenges of high-performance DSPs. The DM642's DSP provides high-speed controller service flexibility and array processor numerical capabilities.

View the full description of the datasheet

 

peculiarity

 

  • High Performance Digital Media Processor (TMS320DM642)
    • 2-, 1.67, 1.39 ns instruction cycle time
    • Clock rates of 500 - 600 - 720 MHz
    • 8 x 32-bit instructions/cycle
    • 4000,4800,5760 MIPS
    • Fully software compatible with the C64x™
  • VelociTI.2™ extends the TMS320C64x™DSP core of VelociTI™ Advanced Very Long Instruction Word VLIW
    • VelociTI.2™ expands 8 highly independent functional units:
      • The ALU (32-/40-Bit) supports single 32-bit, dual-channel 16-bit, or quad 8-bit, arithmetic per clock cycle
      • Two multipliers support four 16-× 16-bit multiplications (32-bit results) per clock cycle or eight 8-× 8-bit multiplications (16-bit results) per clock cycle
    • Load storage architecture, which supports nonalignment
    • 64 32-bit general-purpose registers
    • Reduce the wrapper instruction code size
    • All directive conditions
  • Instruction set features
    • Byte addressing (8-/16-/32-/64-bit data)
    • 8-bit overflow protection
    • Bit field extraction, setting, clearing
    • Normalization, saturation, bit count
    • VelociTI.2™ adds orthogonality

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