MSC8156SVT1000BPerformanceSix-coreDSP
The MSC8156 is based on the industry's highest performance DSP core built in StarCore technology and designed for advanced processing requirements and capabilities for today's high-performance applications in the wireless broadband, medical imaging, aerospace, defense and advanced test and measurement markets.It offers industry-leading performance and power consumption, utilizing 45nm process technology to deliver a single-core device with performance equivalent to 6 GHz in a highly integrated system-on-chip (SoC).The MSC8156 helps device manufacturers create end products and services that integrate more functionality in a smaller footprint.
The MSC8156 DSP offers a high level of performance and integration combined with six fully programmable enhanced SC3850 DSP cores, each running up to 1 GHz.Developed and integrated on-chip by Freescale, the MAPLE-B accelerator supports hardware-accelerated Turbo and Viterbi channel decoding and DFT/IDFT and FFT/IFFT algorithms.The high-performance internal RISC-based QUICC Engine subsystem supports multiple network protocols to guarantee reliable data transmission over packet networks while significantly offloading the processing of DSP cores.
The MSC8156 embeds high-capacity memory and supports a variety of advanced high-speed interface types, including two RapidIO® interfaces, two Gigabit Ethernet interfaces for network communications, one PCI Express® controller, and two high-speed, industry-standard memory interface DDR controllersFour multi-channel TDM interfaces.The MSC8156 is pin-compatible with all MSC825x and MSC815x DSP devices, allowing for a high degree of scalability.
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peculiarity
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Six StarCore SC3850 DSP core subsystems, each with:
SC3850 DSP core, up to 1 GHz
512 KB of unified L2 cache/M2 memory
32 KB I-cache, 32 KB D-cache
Fully programmable 1056 KB M3 Common Memory (SRAM)
MAPLE-B - Highly flexible programmable Turbo and Viterbi decoders support configurable decoding parameters.It can perform Turbo code decoding up to 200 Mbps (6 iterations), or K=9 (zero-tailed) Viterbi decoding up to 115 Mbps
Two DDR 2/3 64-bit SDRAM interfaces at data rates up to 800 MHz
Chip-level arbitration, non-blocking switching fabric, fully pipelined, low latency
High-speed interconnection
4x/1x for PCI Express
Two SGMII
32 GPIOs
16-bit timer
technology
Process: 45nm SOI
Voltage: 1,2.5 volt core, 1.8/1.5-volt I/O
Packing: FC-BPGA (29x29) 1 mm pitch, RoHS compliant
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