AD9510BCPZ

AD9510Provides multiple output clock distribution and integrates an on-chip phase-locked loop (PLL) core. It features low jitter and low phase noise, which can be greatly improvedData convertersof clock performance. Four independent LVPECL clock outputs and four LVDS clock outputs operate at 1.2 GHz and 800 MHz, respectively. The optional CMOS clock output operates at 250 MHz.

The PLL section consists of a programmable reference divider (R), a low noise phase detector (PFD), a precision charge pump (CP), and a programmable feedback divider (N). When an external VCXO or VCO is connected to the CLK2 and CLK2B pins, PLL output frequencies up to 1.6 GHz can be synchronized with the input reference REFIN.

The clock distribution section provides LVPECL outputs and outputs programmable to LVDS or CMOS. Each output has a programmable divider that can be bypassed or set up to an integer divider ratio of up to 32.

The user can change the phase of one clock output relative to the other clock outputs through each divider, and this phase selection function can be used for coarse timing. Some outputs also offer a programmable delay feature with a user-selectable full-scale delay value of up to 10 ns. The fine-tuned delay module is programmed with a 5-bit word and provides 32 usable delay times for the user to choose from.

The AD9510 is ideal for data converter clock applications, utilizing subpicosecond jitter to encode signals for optimal converter performance.

The AD9510 is available in a 64-lead LFCSP package and is specified over the -40°C to +85°C temperature range and can operate from a single 3.3 V supply. If the user wishes to extend the voltage range of the external VCO, a charge pump supply VCP up to 5.5V can be utilized.

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• Low jitter, low phase noise clock distribution
• Provides clocks for high-speed ADC, DAC, DDS, DDC, DUC, and MxFE converters™
• Wireless infrastructure transceivers
• High-performance instrumentation
• Broadband infrastructure