AD6642BBCZ 双通道中频接收机
The AD6642 is an 11-bit, 200 MSPS, dual intermediate frequency (IF) receiver designed to support multichannel systems in telecom applications requiring high dynamic range performance, low power, and small size.
The device includes two high performancesAnalog-to-digital converters(ADC) and noise shaping requantizer (NSR) digital blocks. Each ADC uses a multistage, differential pipelined architecture with integrated output error correction logic. The first stage of the ADC differential pipeline contains a wide bandwidth switched capacitor sampling network. An integrated reference simplifies design. The duty cycle stabilizer (DCS) compensates for fluctuations in the ADC clock duty cycle, allowing the converter to maintain excellent performance.
The outputs of each ADC are internally connected to the NSR block. Integrated NSR circuitry improves signal-to-noise ratio (SNR) performance in smaller bands within the Nyquist bandwidth. The device supports two different output modes, which can be selected via the external MODE pin or SPI.
If the NSR feature is enabled, the AD6642 can achieve higher SNR performance within a limited portion of the Nyquist bandwidth while maintaining 11-bit output resolution when processing the output of the ADC. The NSR block can be programmed to provide 22% or 33% of the bandwidth of the sample clock. For example, when the sampling clock rate is 185 MSPS, the AD6642 can achieve SNR up to 75.5 dBFS in a bandwidth of 40 MHz in 22% mode; In 33% mode, it can achieve SNR of up to 73.7 dBFS over a bandwidth of 60 MHz.
If the NSR block is disabled, the ADC data is provided directly to the output with 11-bit resolution. In this mode of operation, the AD6642 is capable of achieving SNR up to 66.5 dBFS over the entire Nyquist bandwidth. Therefore, the AD6642 can be used in telecom applications such as digital predistortion observation paths that require wider bandwidth.
After digital signal processing, multiplexed output data is routed to two 11-bit output ports with a maximum data rate of 400 Mbps (DDR). These outputs are set to 1.8 V LVDS and support ANSI-644 levels. The AD6642 receiver is capable of digitizing a wide IF spectrum. Each receiver is designed to receive different antennas simultaneously. This IF sampling architecture significantly reduces the cost and complexity of the device compared to traditional analog techniques or less integrated digital methods.
Flexible shutdown options can significantly reduce power consumption. Programming of device setup and control is accomplished using a 3-wire SPI-compatible serial interface; The interface offers multiple modes of operation to support board-level system testing. The AD6642 is available in a 144-lead lead-free 10 mm × 10 mm chip scale ball grid array (CSP_BGA) package and is RoHS qualified and specified over the industrial temperature range of −40°C to +85°C.
apply
- correspondence
- Diversity radio and smart antenna (MIMO) systems
- Multi-mode digital receiver (3G)
- WCDMA、LTE、CDMA2000
- WiMAX、TD-SCDMA
- I/Q demodulation system
- Universal software defined radio