AD6642BBCZRL Dual-channel IF receiver
The AD6642 is an 11-bit, 200 MSPS, dual-channel intermediate frequency (IF) receiver designed to support multi-channel systems in telecom applications that require high dynamic range performance, low power consumption, and small form factor.
The device includes two high-performance analog-to-digital converters (ADCs) and noise shaping requantizer (NSR) digital modules. Each ADC adopts a multi-level, differential pipeline architecture and integrates output error correction logic. The first stage of the ADC differential pipeline contains a wide bandwidth switching capacitor sampling network. Integrated voltage reference simplifies design. The duty cycle stabilizer (DCS) compensates for fluctuations in the ADC clock duty cycle, allowing the converter to maintain excellent performance.
The outputs of each ADC are internally connected to the NSR module. Integrated NSR circuitry improves signal-to-noise ratio (SNR) performance in smaller frequency bands within Nyquist's bandwidth. The device supports two different output modes, which can be selected via an external MODE pin or SPI.
When NSR enabled, the AD6642 can achieve higher SNR performance over a limited partial Nyquist bandwidth while maintaining 11-bit output resolution when processing the ADC's output. The NSR module can be programmed to provide 22% or 33% of the bandwidth of the sampling clock. For example, the AD6642 can achieve an SNR of up to 75.5 dBFS over 40 MHz bandwidth in 22% mode when the sampling clock rate is 185 MSPS; In 33% mode, it can achieve SNR up to 73.7 dBFS over 60 MHz bandwidth.
If the NSR module is disabled, the ADC data is provided directly to the output at 11-bit resolution. In this operating mode, the AD6642 is capable of achieving an SNR of up to 66.5 dBFS over the entire Nyquist bandwidth. As a result, the AD6642 can be used in telecommunications applications such as digital predistortion observation paths that require wider bandwidth.
After digital signal processing, the multiplexed output data is routed to two 11-bit output ports with a maximum data rate of 400 Mbps (DDR). These outputs are set to 1.8 V LVDS and support ANSI-644 levels. The AD6642 receiver is capable of digitizing a wide midrange spectrum. The receivers are designed to receive different antennas synchronously. This IF sampling architecture significantly reduces device cost and complexity compared to traditional analog techniques or less integrated digital methods.
Flexible shutdown options can significantly reduce power consumption. Programming of device setup and control is done using a three-wire SPI-compatible serial interface. The interface provides multiple operating modes to support board-level system testing. The AD6642 is available in a 144-pin, lead-free 10 mm × 10 mm chip-scale ball grid array (CSP_BGA) package and is RoHS compliant and rated for an industrial temperature range of −40°C to +85°C.
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- 通信
- 分集无线电和智能天线(MIMO)系统
- 多模式数字接收器(3G)
- WCDMA、LTE、CDMA2000
- WiMAX、TD-SCDMA
- I/Q解调系统
- 通用软件无线电