AD6659-80EBZ 高能性模数converter
AD6659是一款混合信号双通道中频接收机,支持需要两条接收机信号路径的无线电拓扑结构,例如主信号/分集通道或直接变频。该通信系统处理器由两个高能性模数转换器(ADC)和噪声整形再量化器(NSR)数字模块组成。AD6659专为支持各种需要高动态范围性能和小尺寸的通信应用而设计。
高动态范围ADC内核采用多级、差分流水线架构,并集成了输出纠错逻辑。各ADC的差分流水线第一级采用宽带宽开关电容采样网络。集成基准电压源可简化设计。
各ADC输出从内部连接至NSR模块。集成NSR电路可以改善奈奎斯特区域内的小频段SNR使能NSR特性后,ADC输出经过处理,增强了AD6659在奈奎斯特带宽有限区域内的SNR性能,同时可以保持12位输出分辨率。NSR模块通过编程可提供采样时钟20%的带宽。例如,采样时钟速率为80 MSPS时,AD6659对9.7 MHz AIN下的16 MHz带宽最高可实现81.5 dBFS SNR。
禁用NSR模块后,ADC数据直接提供至输出,输出分辨率为12位。在此模式下,AD6659对整个奈奎斯特带宽最高可实现72 dBFS SNR。
经过数字处理,输出数据路由至两个支持1.8 V或3.3 V CMOS电平的12位输出端口。AD6659接收机可对宽频谱的中频频率进行数字化处理。每个接收机均设计成可同时接收主通道和分集通道。与传统模拟技术或集成度较低的数字方法相比,这种中频采样架构大大降低了器件成本和复杂性。
AD6659还可选用集成直流失调校正和正交误差校正(QEC)模块,用于校正两个通道之间的增益和相位失配。在直接变频接收机等复数信号处理应用中,此功能模块可发挥重要作用。
The ADC includes features that provide optimal flexibility and minimal system cost, such as programmable clock and data alignment, and generation of programmable digital test patterns. Available digital test codes include built-in fixed and pseudo-random codes, as well as user-defined test codes input via the serial port interface (SPI).
A differential clock input is used to control all internal conversion cycles. An optional duty cycle stabilizer (DCS) is used to compensate for large clock duty cycle fluctuations while maintaining excellent overall ADC performance.
The digital output data is formatted as offset binary, gray code, or twos complement. Each ADC channel has a data output clock (DCO) to ensure that the receive logic has the correct latch timing. The device supports both 1.8 V and 3.3 V CMOS levels, and the output data can be multiplexed on a single output bus.
AD6659采用64引脚LFCSP封装,符合RoHS标准,额定温度范围为−40°C至+85°C工业温度范围。
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- correspondence
- Diversity radio system
- Multi-mode digital receiver
3G, W-CDMA, LTE, CDMA2000, TD-SCDMA, MC-GSM- I/Q demodulation system
- Smart antenna system
- Battery-powered meter
- Universal software defined radio
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Features and benefits
- 每通道12位、80 MSPS输出数据速率
- 1.8 V 模拟电源供电(AVDD)
- 1.8 V 至3.3 V输出电源(DRVDD)
- 集成噪声整形再量化器(NSR)
- 集成正交纠错(QEC)
- 使能NSR时的性能
16 MHz频带内信噪比(SNR) = 81 dBFS,80 MSPS下最高30 MHz
- 禁用NSR后的性能
信噪比(SNR) = 72 dBFS,80 MSPS下最高70 MHz
无杂散动态范围(SFDR) = 90 dBc,80 MSPS下最高70 MHz输入
- 低功耗:每通道98 mW (80 MSPS)
- Differential input, 700 MHz bandwidth
- On-chip reference and sample-and-hold circuitry
- 2 V峰峰值差分模拟输入
- Serial port control options
(详情请参考数据手册)