AD6659-80EBZ high-performance analog-to-digital converter
The AD6659 is a mixed-signal dual-channel IF receiver that supports radio topologies that require two receiver signal paths, such as main/diversity channels or direct frequency conversion. The communication system processor consists of two high-performance analog-to-digital converters (ADCs) and noise shaping requantizer (NSR) digital modules. The AD6659 is designed to support a wide range of communication applications that require high dynamic range performance and small form factor.
The high dynamic range ADC core adopts a multi-level, differential pipeline architecture and integrates output error correction logic. The first stage of the differential pipeline of each ADC adopts a wide-bandwidth switching capacitor sampling network. Integrated voltage reference simplifies design.
Each ADC output is internally connected to the NSR module. The integrated NSR circuit improves the small-band SNR-enabled NSR characteristics in the Nyquist region, and the ADC output is processed to enhance the SNR performance of the AD6659 in the Nyquist bandwidth-limited region while maintaining 12-bit output resolution. The NSR module is programmed to provide 20% of the bandwidth of the sample clock. For example, the AD6659 can achieve up to 81.5 dBFS SNR for 16 MHz bandwidth at 9.7 MHz AIN at a sampling clock rate of 80 MSPS.
When the NSR module is disabled, ADC data is fed directly to the output with an output resolution of 12 bits. In this mode, the AD6659 achieves up to 72 dBFS SNR for the entire Nyquist bandwidth.
After digital processing, the output data is routed to two 12-bit output ports that support either 1.8 V or 3.3 V CMOS levels. The AD6659 receiver digitizes midrange frequencies across a wide spectrum. Each receiver is designed to receive both the main and diversity channels. This IF sampling architecture significantly reduces device cost and complexity compared to traditional analog techniques or less integrated digital methods.
The AD6659 also has an integrated DC offset correction and quadrature error correction (QEC) module to correct for gain and phase mismatch between the two channels. This function module can play an important role in complex signal processing applications such as direct conversion receivers.
The ADC has a variety of built-in features that allow for optimal device flexibility and minimal system cost, such as programmable clock and data alignment, generation of programmable digital test codes, and more. Available digital test codes include built-in fixed and pseudo-random codes, as well as user-defined test codes entered via the Serial Port Interface (SPI).
A differential clock input is used to control all internal conversion cycles. An optional duty cycle stabilizer (DCS) is used to compensate for large clock duty cycle fluctuations while maintaining excellent overall ADC performance.
The digital output data format is offset binary, gray code, or binary complement. Each ADC channel has a data output clock (DCO) to ensure that the receive logic has the correct latching timing. The device supports both 1.8 V and 3.3 V CMOS levels, and the output data can be multiplexed on a single output bus.
The AD6659 is available in a 64-pin LFCSP package, is RoHS compliant, and is rated for an industrial temperature range of −40°C to +85°C.
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- 通信
- 分集无线电系统
- 多模式数字接收机
3G, W-CDMA, LTE, CDMA2000, TD-SCDMA, MC-GSM
- I/Q 解调系统
- 智能天线系统
- 电池供电仪表
- 通用软件无线电
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Features and Benefits:
- 每通道12位、80 MSPS输出数据速率
- 1.8 V 模拟电源供电(AVDD)
- 1.8 V 至3.3 V输出电源(DRVDD)
- 集成噪声整形再量化器(NSR)
- 集成正交纠错(QEC)
- 使能NSR时的性能
16 MHz频带内信噪比(SNR) = 81 dBFS，80 MSPS下最高30 MHz
- 禁用NSR后的性能
信噪比(SNR) = 72 dBFS，80 MSPS下最高70 MHz
无杂散动态范围(SFDR) = 90 dBc，80 MSPS下最高70 MHz输入
- 低功耗：每通道98 mW (80 MSPS)
- 差分输入、700 MHz带宽
- 片内基准电压源和采样保持电路
- 2 V峰峰值差分模拟输入
- 串行端口控制选项
（详情请参考数据手册）