AD6672BCPZ-250

• Product Introduction

AD6672BCPZ-250 IF receiver

The AD6672 is an 11-bit IF receiver with a sample rate of up to 250 MSPS designed to provide a solution for low-cost, small-size, wide-bandwidth, multi-function communication applications.  

This ADC core adopts a multi-level, differential pipeline architecture and integrates output error correction logic. The ADC has a wide bandwidth input and supports a variety of user-selectable input ranges. Integrated voltage reference simplifies design. The duty cycle stabilizer can be used to compensate for fluctuations in the ADC clock duty cycle, allowing the converter to maintain excellent performance.

The core output of this ADC is internally connected to the Noise Shaping Requantizer (NSR) module. The device supports two output modes, which can be selected via the Serial Port Interface (SPI). When the NSR feature is enabled, the AD6672 can achieve higher SNR performance in a limited Nyquist bandwidth region while maintaining 11-bit output resolution when processing the ADC's output. The NSR module can be programmed to provide up to 33% of the sampling clock bandwidth. For example, with a sample clock rate of 250 MSPS, the AD6672 achieves an SNR of up to 73.6 dBFS at 82 MHz bandwidth and 185 MHz fIN.

If the NSR module is disabled, ADC data is provided directly to the output at an output resolution of 11 bits. In this operating mode, the AD6672 is capable of achieving an SNR of up to 66.6 dBFS over the entire Nyquist bandwidth.

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• 通信
• 分集无线电和智能天线(MIMO)系统
• 多模式数字接收机(3G)WCDMA、LTE、CDMA2000 WiMAX、TD-SCDMA
• I/Q解调系统
• 通用软件无线电