AD7266ASU

Both the conversion process and the data acquisition process use standard control inputs and can be easily interfaced with microprocessors or DSPs. The input signal is sampled on the falling edge of CS, where the conversion is initiated simultaneously. The conversion time depends on the SCLK frequency. The AD7266 uses advanced design techniques to achieve very low power consumption at high throughput. It operates at 5 V and has a throughput of 2 MSPS while consuming only 4 mA maximum. In normal operating mode, the device also features flexible power/throughput management due to ultra-low quiescent current consumption levels.

Its analog input range is 0 V to V_REF (or 2 × V.)_REF ) to choose between standard binary or twos complement output encoding. The AD7266 has an on-chip reference voltage of 2.5 V, which can be exceeded when an external reference voltage is required, with an external reference range of 100 mV to V_DD 。 The AD7266 is available in both 32-lead LFCSP and 32-lead TQFP packages.Product Focus

1. Two complete ADC functions enable simultaneous sampling and conversion of two channels. Each ADC can be programmed to be set to three all/pseudo differential pairs or six single-ended inputs. The conversion results of the two channels can be obtained simultaneously by independent data lines, and if only one serial port is available, the conversion results can be obtained sequentially through one data line.
2. High throughput and low power consumption. The AD7266 has a throughput of 2 MSPS and consumes only 9 mW maximum power at 3 V.
3. The AD7266 is also available from standard 0 V to V_REF Input range and 2 × V_REF Input range.
4. No pipeline delay. The device uses two standard successive approximation ADCs to pass.CSInput and one-time conversion control enables precise control of sampling time.