AD9250-250EBZ 14-bit, 170 MSPS/250 MSPS, JESD204B, dual analog-to-digital converter
The AD9250 is a dual 14-bit ADC with a maximum sample rate of 250 MSPS designed to provide a solution for low cost, small size, wide bandwidth, versatile communication applications.
The ADC core uses a multistage, differential pipelined architecture with integrated output error correction logic. The ADC core has wide bandwidth inputs that support a variety of user-selectable input ranges. An integrated reference simplifies design. A duty cycle stabilizer can be used to compensate for fluctuations in the ADC clock duty cycle, allowing the converter to maintain excellent performance. The JESD204B high-speed serial interface reduces board routing requirements and reduces the number of pins required for the receiving device.
By default, ADC output data is routed directly to two JESD204B serial output channels, which are set to CML levels. The four modes support any combination of M = 1 or 2 (single or dual converter) and L = 1 or 2 (single or dual). In dual ADC mode, data can be sent over two channels at a maximum sample rate of 250 MSPS. However, if data is sent over one channel, only sample rates up to 125 MSPS are supported. The device provides synchronous inputs (SYNCINB± and SYSREF ±).
Flexible shutdown options can significantly reduce power consumption when needed. Each channel supports programmable overrange level detection through a dedicated fast sense pin.
Setup and control programming is accomplished using a 3-wire SPI-compatible serial interface.
The AD9250 is available in a 48-lead LFCSP package and is specified over the industrial temperature range of −40°C to +85°C. This product is protected by a U.S. patent.
Product features
- Integrated dual, 14-bit, 170 MSPS/250 MSPS ADC.
- The configurable JESD204B output module supports sample rates up to 5 Gbps per channel.
- An on-chip phase-locked loop (PLL) allows the user to provide a single ADC sample clock, which corresponds to a JESD204B data rate clock that is generated by multiplying the PLL by the ADC sample clock.
- Supports optional RF clock input to simplify system board design.
- The patented differential inputs maintain excellent signal-to-noise ratio (SNR) performance at input frequencies up to 400 MHz.
- Operates from a single 1.8 V supply.
- The standard serial port interface (SPI) supports various product features and functions such as control clock DCS, power-down mode, test mode, reference mode, overrange fast detection, and serial output configuration.
apply
• Diversity radio systems
• Multi-mode digital receiver (3G)
TD-SCDMA、WiMax、WCDMA、CDMA2000、GSM、EDGE、LTE
• HFC digital reverse path receiver
• I/Q demodulation system
• Smart antenna system
• Electronic test and measurement equipment
• Radar receivers
• COMSEC radio architecture
• IED detection/jamming system
• General purpose software defined radio
• Broadband data applications
Microchip Centennial Electronic Technology (Shenzhen) Co., Ltd
Address: Shenzhen Futian District Huaqiang Road Huaqiang Plaza A Block 13H
Tel: 0755-83591082
Fax: 0755-83591083
Q Q：1051085817
//www.chip100.com/