AD9262-5EBZ

• Product introduction

AD9262-5EBZ 16-bit, 2.5 MHz/5 MHz/10 MHz, 30 MSPS to 160 MSPS, dual continuous-time sigma-delta ADCs

The AD9262 is a dual, 16-bit analog-to-digital converter (ADC) using a continuous-time sigma-delta architecture that achieves a dynamic range of 86 dB over a 10 MHz input bandwidth. The unique integrated functions and features of the continuous-time sigma-delta architecture greatly simplify its performance and require very few external components.

The AD9262 has a resistive input impedance that significantly reduces the requirements for the driver amplifier. In addition, a 32x oversampled fifth-order continuous time loop filter significantly attenuates out-of-band signals and aliasing, eliminating the need for an external filter at the input.

An external clock input or an integrated integer-N phase-locked loop (PLL) provides the 640 MHz internal clock required for an oversampled continuous-time sigma-delta modulator. On-chip decimation filters and sample rate converters reduce the modulator data rate from 640 MSPS to a user-defined output data rate (30 MSPS to 160 MSPS), enabling a more efficient and straightforward interface.

The AD9262 integrates a dc correction and quadrature estimation block to correct for gain and phase mismatches between the two channels. This function block can play an important role in complex signal processing applications such as direct conversion receivers.

The digital output data is formatted as offset binary, gray code, or twos complement. The data clock output (DCO) is used to ensure that the receive logic is operating in the correct timing. The AD9262 also adds a feature that simplifies board routing by interleaving Channel A and Channel B data on a 16-bit bus.

Available in 2.5 MHz, 5 MHz, and 10 MHz bandwidth options, the ADC operates from a 1.8 V analog supply and a 1.8 V to 3.3 V digital supply and consumes 675 mW. The AD9262 is available in a 64-lead LFCSP package and is specified over the industrial temperature range of −40°C to +85°C.

Product Focus

1. The continuous-time sigma-delta architecture effectively achieves high dynamic range and wide bandwidth.
2. The passive input structure reduces the requirements for the driver amplifier or eliminates the driveramplifier。
3. A 32x oversampling ratio and a higher-order loop filter provide excellent alias rejection, reducing the need for anti-aliasing filters or eliminating anti-aliasing filters.
4. An integrated decimation filter, sample rate converter, PLL clock multiplier, and voltage reference make the device easy to use.
5. It operates from a single 1.8 V analog supply and a 1.8 V to 3.3 V output supply.
6. The standard serial port interface (SPI) supports a variety of product features and functionality.

apply

• Baseband quadrature receivers: CDMA2000, WCDMA, multicarrier GSM/EDGE, 802.16x, LTE
• Quadrature sampling instrument
• Medical equipment
• Radio Detection and Ranging (RADAR)