AD9510BCPZ

The PLL section consists of a programmable reference crossover (R), a low-noise frequency discriminator (PFD), a precision charge pump (CP), and a programmable feedback divider (N). PLL output frequencies up to 1.6 GHz can be synchronized with the input reference REFIN when an external VCXO or VCO is connected to the CLK2 and CLK2B pins.

The clock assignment section provides LVPECL outputs and outputs that can be programmed as LVDS or CMOS. Each output has a programmable crossover that can be bypassed or set to an integer crossover ratio of up to 32.

The user can change the phase of one clock output relative to the other clock outputs through each crossover, and this phase selection function can be used for timing coarseness. Some outputs also offer programmable delay features with user-selectable full-scale delay values of up to 10 ns. The fine-tuned delay module is programmed with a single 5-bit word and provides 32 available delay times for the user to choose from.

The AD9510 is ideal for data converter clock applications, utilizing sub-picosecond jitter encoded signals for optimal converter performance.

The AD9510 is available in a 64-pin LFCSP package with a temperature range of -40°C to +85°C and can be operated from a single 3.3 V supply. If the user wishes to extend the voltage range of the external VCO, a charge pump supply VCP of up to 5.5V can be utilized.

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