AD9512Multiple output clock distribution is available for input signals up to 1.6 GHz. It features low jitter and low phase noise, which can be greatly improvedData convertersof clock performance.
Three independent LVPECL clock outputs and two LVDS clock outputs operate at 1.2 GHz and 800 MHz, respectively. The optional CMOS clock output operates at 250 MHz. Each output has a programmable divider that can be bypassed or set up to an integer divider ratio of up to 32.
The user can change the phase of one clock output relative to the other clock outputs through each divider, and this phase selection function can be used for coarse timing. One output also provides a programmable delay feature with a user-selectable full-scale delay value of up to 10 ns. The fine-tuned delay module is programmed with a 5-bit word and provides 32 usable delay times for the user to choose from.
Ideal for data converter clock applications, the AD9512 uses subpicosecond jitter to encode signals for optimal converter performance.
The AD9512 is available in a 48-lead LFCSP package and is specified over the -40°C to +85°C temperature range and can operate from a single 3.3 V supply.
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- Low jitter, low phase noise clock distribution
- Provides clocks for high-speed ADC, DAC, DDS, DDC, DUC, and MxFE converters™
- Wireless infrastructure transceivers
- High-performance instrumentation
- Broadband infrastructure