The AD9512 provides multiple output clock assignments with input signals up to 1.6 GHz. It has low jitter and low phase noise, which can greatly improve the clock performance of the data converter.
The three independent LVPECL clock outputs and two LVDS clock outputs operate at 1.2 GHz and 800 MHz, respectively. The optional CMOS clock output operates at 250 MHz. Each output has a programmable crossover that can be bypassed or set to an integer crossover ratio of up to 32.
The user can change the phase of one clock output relative to the other clock outputs through each crossover, and this phase selection function can be used for timing coarseness. The 1-channel output also offers programmable delay features with user-selectable full-scale delay values up to 10 ns. The fine-tuned delay module is programmed with a single 5-bit word and provides 32 available delay times for the user to choose from.
The AD9512 is ideal for data converter clock applications, utilizing sub-picosecond jitter encoded signals for optimal converter performance.
The AD9512 is available in a 48-pin LFCSP package with a temperature range of -40°C to +85°C and can be operated from a single 3.3 V supply.
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低抖动、低相位噪声时钟分配
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