AD9513It is a triple output clock distribution IC with low jitter and low phase noise for optimal performanceData convertersPerformance. The device is also suitable for other applications where phase noise and jitter are critical.
Three independent clock outputs can be set to LVDS or CMOS levels. In LVDS mode, the output operates at 800 MHz; In CMOS mode, the output operates at 250 MHz.
Each output has a programmable divider, which can set the integer divider ratio of 1~32. The phase of one clock output relative to the other clock outputs can be programmed through the divider phase selection function as coarse timing.
One of the outputs provides a delay unit with three selectable full-scale delay values (1.5 ns, 5 ns, and 10 ns), each with 16 steps of fine tuning.
The AD9513 requires no external controller to operate or set up. The device is programmed through 11 pins (S0~S10) and 4 logic levels. The programming pin is internally biased to 1/3 VS. The VREF pin provides a 2/3 VS level. VS (3.3 V) and GND (0 V) provide two additional logic levels.
The AD9513 is ideal for data converter clock applications and encodes signals using subpicosecond jitter for optimal converter performance.
The AD9513 is available in a 32-lead LFCSP package with a single 3.3 V supply operation over the −40°C~+85°C temperature range.
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