The AD9523 provides low power, multiple output clock distribution with low jitter performance, and includes an on-chip phase-locked loop (PLL) and voltage-controlled oscillator (VCO). The on-chip VCO is tuned over a frequency range of 3.6 GHz to 4.0 GHz.
The AD9523 is designed to meet the clocking requirements of long-term evolution (LTE) and multicarrier GSM base station designs. It relies on external VCXOs to remove reference jitter to meet stringent low phase noise requirements for acceptable data converter signal-to-noise ratio (SNR) performance.
Input receivers, oscillators, and zero-delay receivers support both single-ended and differential operation. When connected to the recovered system reference clock and VCXO, the device produces 14 low-noise outputs from 1 MHz to 1 GHz, as well as a dedicated buffered output from the input PLL (PLL1). The frequency and phase of one clock output relative to the other can be changed by the divider phase selection function, which is used as a jitter-free coarse timing adjustment in increments equivalent to the period of the VCO output signal.
The in-package EEPROM can be programmed through a serial interface to store user-defined register settings for power-up and chip reset.
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- LTE and multicarrier GSM base stations
- Wireless and broadband infrastructure
- Medical instruments
- Provides clocks for high-speed ADC, DAC, DDS, DDC, DUC, MxFE
- Low jitter, low phase noise clock distribution
- Clock generation and conversion for SONET, 10Ge, 10G FC, and other 10 Gbps protocols
- Forward Error Correction (G.710)
- High-performance wireless transceivers
- Automated Test Equipment (ATE) and high-performance instrumentation