AD9523提供低功耗、多路输出时钟分配功能，具有低抖动性能，还配有片内集成锁相环(PLL)和电压控制振荡器(VCO)。片内VCO的调谐频率范围为3.6 GHz至4.0 GHz。
The AD9523 is designed to meet the clock requirements of long-term evolution (LTE) and multi-carrier GSM base station designs. It relies on an external VCXO to clear reference jitter to meet stringent low phase noise requirements for acceptable data converter signal-to-noise ratio (SNR) performance.
The input receiver, oscillator, and zero-delay receiver support both single-ended and differential operation. When connected to a recovered system reference clock and VCXO, the device produces 14 low-noise outputs from the 1 MHz to 1 GHz range, as well as a dedicated buffered output from the input PLL (PLL1). The frequency and phase of one clock output relative to the other clock output can be changed by the crossover phase selection function, which is used as jitter-free timing coarse tuning in increments equivalent to the period of the VCO output signal.
The in-package EEPROM can be programmed via a serial interface to store user-defined register settings for power-up and chip reset.
应用
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LTE和多载波GSM基站
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无线和宽带基础设施
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医疗仪器
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为高速ADC、DAC、DDS、DDC、DUC、MxFE提供时钟
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低抖动、低相位噪声时钟分配
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SONET、10Ge、10G FC和其它10 Gbps协议的时钟产生和转换
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前向纠错(G.710)
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高性能无线收发器
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自动测试设备(ATE)和高性能仪器仪表