The AD9528 is a dual-stage PLL with an integrated JESD204B SYSREF generator for multi-device synchronization. The first-stage phase-locked loop (PLL) (PLL1) enables input voltage reference conditioning by reducing the jitter of the system clock. The second stage PLL (PLL2) provides high-frequency clocking, which enables low integral jitter from the clock output driver as well as low wideband noise. The external VCXO provides the low-noise reference required by the PLL2 to meet demanding phase noise and jitter requirements for acceptable performance. The on-chip VCO has a tuning frequency range of 3.450 GHz to 4.025 GHz. The integrated SYSREF generator outputs single, N times, or continuous signals and is synchronized with the PLL1 and PLL2 outputs to align the timing of multiple devices.
The AD9528 produces two outputs (Output 1 and Output 2) up to 1.25 GHz and 12 outputs up to 1 GHz, each of which can be configured to output directly from PLL1, PLL2, or an internal SYSREF generator. Each of the 14 output channels contains a crossover with digital phase coarse tuning and an analog fine-tuning phase delay module, allowing for a high degree of flexibility in timing alignment for all 14 outputs. The AD9528 can also be used as a flexible, dual-channel input buffer to enable the distribution of 14-channel device clocks and/or SYSREF signals. When powered on, the AD9528 sends VCXO signals directly to outputs 12 and 13 to be used as power-up ready clocks.
Note that throughout the datasheet, the dual-function pin names refer to the applicable relevant functions.
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高性能无线收发器
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LTE和多载波GSM基站
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无线和宽带基础设施
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医疗仪器
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为高速ADC、DAC、DDS、DDC、DUC、MxFE提供时钟；支持JESD204B
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低抖动、低相位噪声时钟分配
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自动测试设备(ATE)和高性能仪器仪表