AD9650-65

• Product introduction

AD9650-65 14-bit, 170 MSPS/250 MSPS, JESD204B analog-to-digital converter

The AD9683 is a 14-bit ADC with a maximum sampling rate of 250 MSPS designed to provide a solution for low cost, small size, wide bandwidth, versatile communication applications.

The ADC core uses a multistage, differential pipelined architecture with integrated output error correction logic. The ADC core has wide bandwidth inputs that support a variety of user-selectable input ranges. An integrated reference simplifies design. A duty cycle stabilizer can be used to compensate for fluctuations in the ADC clock duty cycle, allowing the converter to maintain excellent performance. The JESD204B high-speed serial interface reduces board routing requirements and reduces the number of pins required for the receiving device.

The ADC output data is fed directly to the JESD204B serial output channel. These outputs are set to CML levels. Data can be sent over the channel at a maximum sample rate of 250 MSPS, resulting in a channel rate of 5 Gbps. The device provides synchronous inputs (SYNCINB± and SYSREF ±).

Flexible power-down options can significantly reduce power consumption when needed. Programmable overrange level detection is supported via a dedicated fast detect pin.

Setup and control programming is accomplished using a 3-wire SPI-compatible serial interface.

The AD9683 is available in a 32-lead LFCSP package and is specified over the industrial temperature range of −40°C to +85°C. This product is protected by a U.S. patent.

Product features

1. Integrated 14-bit, 170 MSPS/250 MSPS ADC.
2. The configurable JESD204B output module supports lane rates up to 5 Gbps.
3. An on-chip phase-locked loop (PLL) allows the user to provide a single ADC sample clock, which corresponds to a JESD204B data rate clock that is generated by multiplying the PLL by the ADC sample clock.
4. Supports optional RF clock input to simplify system board design.
5. The patented differential inputs maintain excellent signal-to-noise ratio (SNR) performance at input frequencies up to 400 MHz.
6. Operates from a single 1.8 V supply.
7. The standard serial port interface (SPI) supports a variety of product features and functions, such as control clock DCS, power-down mode, test mode, reference mode, overrange fast detection, and serial output configuration.

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• correspondence
• Diversity radio system
• Multi-Mode Digital Receiver (3G)
  TD-SCDMA、WiMAX、WCDMA、CDMA2000、GSM、EDGE、LTE
• DOCSIS 3.0 CMTS upstream receive path
• HFC digital reverse path receiver
• Smart antenna system
• Electronic test and measurement equipment
• Radar receiver
• COMSEC radio architecture
• IED detection/interference system
• Universal software defined radio
• Broadband data applications
• Ultrasound equipment
• Features and benefits
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  The JESD204B Subclass 0 or Subclass 1 encodes serial digital output
  Signal-to-noise ratio (SNR): 70.6 dBFS (185 MHz AIN, 250 MSPS)
  Spray free dynamic range (SFDR): 88 dBc (185 MHz AIN, 250 MSPS)
  Total power consumption:
  434 mW (250 MSPS)
  1.8 V supply voltage
  1 to 8 integer input clock divider
  Sample rates up to 250 MSPS
• IF sampling frequency up to 400 MHz
  Analog-to-digital converters (ADCs) have an internal voltage reference
  Flexible analog input range
  -- 1.4 V p-p to 2.0 V p-p
  (nominal 1.75 V p-p)
  ADC Clock Duty Cycle Stabilizer (DCS)
  Serial port control
  Energy-saving power-down mode

Microchip Centennial Electronic Technology (Shenzhen) Co., Ltd

Address: Shenzhen Futian District Huaqiang Road Huaqiang Plaza A Block 13H

Tel: 0755-83591082

Fax: 0755-83591083

Q Q：1051085817

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