AD9681BBCZRL7-125

The ADC requires a single 1.8 V supply and an LVPECL/CMOS/LVDS compatible sample rate clock signal to maximize its performance. No external reference or driver is required to meet many application needs.

The AD9681 automatically multiplies the sample rate clock to generate the appropriate LVDS serial data rate. It provides data clock outputs (DCO±1, DCO±2) for capturing data at the output, and frame clock outputs (FCO±1, FCO±2) for sending new output byte signals. Support independent shutdown of each channel; With all channels disabled, the typical power consumption of the device is less than 2 mW.

The ADC has a variety of built-in features that allow for optimal device flexibility and minimal system cost, such as programmable clock and data alignment, generation of programmable digital test codes, and more. Available digital test codes include built-in fixed and pseudo-random codes, as well as user-defined test codes entered via the Serial Port Interface (SPI).

The AD9681 is available in a RoHS-compliant 144-pin CSP-BGA package. Rated for the −40°C to +85°C industrial temperature range. The product is protected by a U.S. patent.

Product features: 

1. 小尺寸。一个小型10 mm × 10 mm封装中集成8个ADC。
2. 低功耗。器件每通道消耗110 mW (125 MSPS)，功率选项可调整
3. 易于使用。数据时钟输出（DCO±1、DCO±2）工作频率高达500 MHz，支持双倍数据速率(DDR)操作。
4. 使用灵活。SPI控制提供丰富灵活的特性，可满足各种特定系统的需求。

apply

• 医疗成像
• 通信接收机
• 多通道数据采集