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AD9861BCPZ-50
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AD9861BCPZ-50

  • 所属类别:高速/宽带编解码器和模拟前端High-speed logic
  • 产品名称:10位混合信号前端(MxFE®)处理器
  • 厂商:Analog Devices
  • 生产批号:15+
  • 封装:64 ld LFCSP
  • 库存状态:有库存
  • 库存量:980
  • 最低订购量:1
  • 详细资料:点击查找AD9861BCPZ-50的pdf资料
  • 点击询价
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  • Product Introduction

Advantages and features:

  • 接收路径内置双通道10位analog-to-digital converter,支持内部或外部基准电压源接入,提供50 MSPS和80 MSPS两种型号
  • 发射路径内置双通道10位、200 MSPS数模转换器,提供1x、2x或4x插值和可编程增益控制
  • 内部时钟分配模块包括可编程锁相环(PLL)与时序产生电路,允许单一基准时钟操作
  • 灵活的20位I/O数据接口,允许在半双工模式下进行各种交错或非交错数据传输,以及在全双工模式下进行交错数据传输
  • 可通过SPI兼容端口或MODE选择引脚进行配置
  • 独立的接收和发射关断控制引脚
  • 64引脚LFCSP封装
    (尺寸:9 mm x 9 mm)
  • 3个可配置辅助转换器引脚

Product Details:

The AD9861 is one of the MxFE series of integrated converters® for the communications market. It has a built-in dual-channel 10-bit analog-to-digital converter (ADC) and a dual-channel 10-bit digital-to-analog converter (TxDAC® converter). Available in 50 and 80 speed ratings, the 50 rating is optimized for ADC sampling rates of 50 MSPS and below, and the 80 rating is optimized for ADC sampling rates between 50 MSPS and 80 MSPS. The dual-channel TxDAC converter operates at frequencies up to 200 MHz and has a built-in bypass 2x or 4x interpolation filter. Three auxiliary converters are provided simultaneously to provide the required system-level control voltage or to monitor system signals. All devices are optimized for low power consumption and small form factor, providing cost-effective solutions for the broadband communications market.


The AD9861 uses one input clock pin (CLKIN) to generate all system clocks. ADC and TxDAC converter clocks are generated within a timing generation module that utilizes user-programmable options such as crossover circuitry, PLL multipliers, and switches.


The flexible bidirectional 20-bit I/O bus is suitable for a variety of custom digital back-ends or open-market DSPs. In a half-duplex system, the interface supports 20-bit parallel transmission or 10-bit interleaved transmission. In a full-duplex system, the interface supports a 10-bit ADC bus with staggered transmission and a 10-bit transmit bus with staggered transmission. The flexible I/O bus reduces the number of pins and reduces the package size.


The AD9861 can be configured with an interface bus using the MODE pin or serial programming interface (SPI) to operate the ADC in low-power mode, configure the TxDAC converter interpolation rate, and control ADC shutdown and TxDAC shutdown. SPI provides additional programming options for TxDAC paths (e.g., gain coarse and fine-tuning, offset control for channel matching) and ADC paths (e.g., internal duty cycle stabilizers, binary complement data formats).


The AD9861 is available in a 64-pin LFCSP package (thin, thin-pitch chip-scale package) with a form factor of just 9 mm x 9 mm and a height of less than 0.9 mm, making it suitable for space-intensive applications such as PCMCIA cards.


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  • 宽带接入
  • 宽带局域网(LAN)
  • 通信(调制解调器)

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