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AD9861BCPZRL-80
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AD9861BCPZRL-80

  • Category:High-speed / wideband codec and analog front end High-speed logic
  • Product Name:10-bit mixed-signal front-end (MxFE)® processor
  • Manufacturers:Analog Devices
  • Production Batch Number:15+
  • Encapsulation:64 ld LFCSP
  • Stock Status:There is stock
  • Stock Quantity:980
  • Minimum order quantity: 1
  • Details:Click here to find pdf information for the AD9861BCPZRL-80
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  • Product introduction

Advantages and features

  • The receive path has built-in dual channel 10-bitsAnalog-to-digital convertersInternal or external reference access is supported and 50 MSPS and 80 MSPS models are available
  • The transmit path includes dual 10-bit, 200 MSPS digital-to-analog converters that provide 1x, 2x, or 4x interpolation and programmable gain control
  • The internal clock distribution block includes a programmable phase-locked loop (PLL) and timing generation circuitry that allows single base clock operation
  • A flexible 20-bit I/O data interface allows a variety of interleaved or non-interleaved data transfers in half-duplex mode and interleaved data in full-duplex mode
  • Configurable via SPI-compatible port or MODE select pin
  • Independent receive and transmit shutdown control pins
  • 64-pin LFCSP package
    (Size: 9 mm x 9 mm)
  • 3 configurable auxiliary converter pins

Product details

The AD9861 is part of the MxFE family of integrated converters® for the communications market. It contains dual 10-bit analog-to-digital converters (ADCs) and dual 10-bit digital-to-analog converters (TxDAC® converters). Available in 50 and 80 speed grades, the 50 grade is optimized for ADC sampling rates of 50 MSPS and below, and the 80 grade is optimized for ADC sampling rates between 50 MSPS and 80 MSPS. The dual TxDAC converter operates at frequencies up to 200 MHz and includes a bypassable 2x or 4x interpolation filter. Three auxiliary converters are provided simultaneously to provide the required system-level control voltage or to monitor system signals. All devices are optimized for low power consumption and small size, providing a cost-effective solution for the wideband communications market.


The AD9861 uses an input clock pin (CLKIN) to generate all system clocks. ADC and TxDAC converter clocks are generated within a sequencing block that utilizes user-programmable options such as divider circuitry, PLL multipliers, and switches.


Flexible bidirectional 20-bit I/O bus for a variety of custom digital back-ends or open market DSPs. In half-duplex systems, the interface supports 20-bit parallel transmission or 10-bit interleaved transmission. In a full-duplex system, the interface supports a 10-bit ADC bus that is interleaved and a 10-bit transmit bus that is interleaved. The flexible I/O bus reduces pin count and package size.


The AD9861 can use the MODE pin or the serial programming interface (SPI) configuration interface bus to run the ADC in low power mode, configure the interpolation rate of the TxDAC converter, and control the ADC shutdown and TxDAC shutdown. SPI provides more programming options for TxDAC paths (e.g., gain coarse and trim, offset control for channel matching) and ADC paths (e.g., internal duty cycle stabilizer, twos complement data format).


AD9861Housed in a 64-pin LFCSP package (low-profile, fine-pitch chip-scale package), it measures only 9 mm x 9 mm and is less than 0.9 mm high, making it suitable for space-intensive applications such as PCMCIA cards.


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  • Broadband access
  • Broadband Local Area Network (LAN)
  • Communication (modem)

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