ADC08D1500CIYB

• Internal sampling and holding
• Single +1.9 V ± 0.1 V operation
• Choice of SDR or DDR output clock
• Interleaved mode has a 2x sample rate
• Multiple ADC synchronization capability
• No code loss guaranteed
• Serial interface for extended control
• Enter fine-tuning and offset for the full-scale range
• Duty cycle corrects the sampling clock

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ADC08D1500 is a dual-channel, low-power, high-performance CMOS analog-to-digital converter with a digitized signal sampling rate of 8 bits and a resolution of up to 1.7 GSPS. Consuming from a single 1.9 volt power supply at 1.5 GSPS to a typical 1.8 watt, this device is guaranteed to be code-free over the entire operating temperature range. The unique folding and interpolation architecture, the design of the fully differential comparator, internal sampling with holding amplifier and self-calibration plan make an innovative design that responds very flat to all dynamic parameters other than Nyquist, producing an input signal with a high ENOB of 748 MHz and a sampling rate of 1.5 GHz while providing 10 -18 The CER output format is binary, with an adjustable common-mode voltage anomaly between 0.8V and 1.2V, and the LVDS digital output is compliant with IEEE 1596.3-1996.

Each converter has a 1:2 multiplexer, feeds two LVDS buses, and the output data rate on each bus is reduced by half the sample rate. The two converters are staggered and used as a single 3 GSPS ADC.

The typical power consumption of the power-down mode converter is less than 3.5 megawatts and 128 leads, thermally resistant to reinforced exposed pads in an LQFP package and works in industrial (-40°C). ≤ T A ≤ 85°C) temperature range.

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• Direct RF downconversion
• Digital oscilloscope
• Satellite set-top box
• Communication system
• Test instruments