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ADC10D040CIVS
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ADC10D040CIVS

  • 所属类别:ADC模数转换器
  • 产品名称:双12位,40 MSPS,600兆瓦内部/外部参考的A / D转换
  • 厂商:NSC
  • 生产批号:09+
  • 封装:QFP
  • 库存状态:有库存
  • 库存量:5000
  • 最低订购量:1
  • 详细资料:点击查找ADC10D040CIVS的pdf资料
  • 点击询价
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  • Product Introduction

peculiarity

  • Complement output format of binary or 2
  • Single power supply
  • Internal sampling and holding
  • Output 2.4V to 5V compatible
  • Power-down mode
  • Pin compatible with ADC12DL066
  • Internal/external references

illustrate

ADC12D040 is a dual-channel, low-power monolithic CMOS analog-to-digital converter capable of converting analog input signals to 12-bit digits at 40 up to and per second (MSPS), as low as possible. The converter uses a differential, pipeline architecture with digital error correction and an on-chip sampling and hold circuit to minimize die size and power consumption while providing excellent dynamic performance. A single 5V supply operates from a 10 MHz input ADC12D040 reaches 10.9 effective bits at 40 MSPS, including a reference current consumption of only 600 megawatts. The downward function power consumption is reduced to 75 megawatts.

The differential input provides the possibility of a full-scale differential input with a swing equal to 2V and a single-ended input. It is recommended to make full use of differential inputs for optimal performance. The digital outputs of the two ADCs can be selected in a separate 12-bit offset binary or 2 complement output data format bus.

For easy interface, the ADC12D040 of the digital output driver power pins can be connected to a separate supply voltage range of 2.4V digital supply voltage, making the output low-voltage system compatible. ADC12D040 speed, resolution, and single power supply make it ideal for a variety of applications.

The device is available in a 64-pin TQFP package and will operate in industrial temperatures from -40°C to +85°C. The evaluation board provides a convenient product evaluation process

Key specifications:

Signal-to-noise ratio (= 10 MHz f)

68 dB (typical)

ENOB (= 10 MHz f)

10.9 bits (typical)

SFDR (= 10 MHz f)

80 dB (typical)

Data delay

6 clock cycles

Supply voltage

+5 V ± 5%

Power consumption, work

 
  • Job

    600 mW (typical)

    Power-down mode

    75 MW (typical)


apply

  • Ultrasound and imaging
  • instrumentation
  • Communication receiver
  • Sonar/radar
  • xDSL
  • Cable modem

ADC10D040CIVS-related ICs include:


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