ADC10D1000CIUT

• Excellent precision and dynamic performance
• Pin compatible with ADC12D1000/1600/1800
• Low power consumption, further reduced at lower Fs
• Internally terminated, buffered, differential analog inputs
• R/W SPI interface extended control mode
• In dual-edge sampling mode, I and Q channel sample two times sample clock rate with one input
• Test the debug output mode of the system
• 15-bit programmable gain and 12-bit plus sign offset
• Programmable T_a.dAdjustment function
• LVDS output 1:1 non-demuxed or 1:2 demuxed
• Multi-chip system with automatic synchronization function
• Single 1.9V ± 0.1V supply
• 292 ball BGA package (27mm x 27mm form factor x 1.27mm ball pitch 2.4mm), no hot water tank required

illustrate

The ADC10D1000/1500 is the latest advance in the nationwide ultrafast ADC family. This low-power, high-performance CMOS analog-to-digital converter samples up to 1.0/1.5 GSPS (non-DES mode) for dual-channel digitized signals or 3.0 GSPS (DES mode) for a single channel with up to 2.0/10-bit resolution. The ADC10D1000/1500 achieve excellent accuracy and dynamic performance while consuming less than 2.8/3.6 watts. Beyond the rated industrial temperature range, the product is packaged in a 292-ball thermally enhanced BGA package with or without lead -40 ° C〜 to +85°C.

After the ADC10D1000/1500 is established, the functions, architecture, and functionality of the 8-bit ADC GHz family. The expanded feature set includes multi-chip synchronization, automatic synchronization, 15 bits Programmable gain and 12-bit plus sign, programmable offset adjustment for each channel. Improved internal tracking and hold amplifiers and extended self-calibration schemes enable a very flat response to all dynamic parameters outside of Nyquist, producing a 100 MHz input signal and 1.0/1.5 9.1/9.0 bit effective bits (ENOB) while providing a 10 GHz sample rate -18 The bit error rate (CER), 1.0/1.5 GSPS dissipated from a single 1.9V supply in a typical 2.77/3.59V non-demultiplexed mode, this device is guaranteed to be free of missing codes over the entire operating temperature range.

Each channel has its own independent DDR data clock, DCLKI and DCLKQ, and in the second stage, both channels are powered on, so that only one data clock can be used to capture all the data, sending the sample clock as input at the same speed. If the 1:2 Demux mode is selected, the second 10-bit LVDS bus becomes active for each channel, and the output data rate is sent out twice slower to relax data acquisition timing requirements. The section can also be used as a single 2.0/3.0 GSPS ADC to sample I or Q inputs. The format of the output can be programmed to offset binary or two's complement and the low voltage differential signaling (LVDS) digital output is compatible with IEEE 1596.3-1996 adjustable common-mode voltage anomalies of 0.8V and 1.2V in order to allow reduced power consumption control back to the aircraft.

Main specifications

(Non-DES mode for non-Demux, FS = 1.0/1.5 GSPS, FIN = 100 MHz)

• Conversion rate

• power consumption

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• Broadband communications
• Data acquisition system
• Digital oscilloscope