ADC10D1500CIUT

• Excellent precision and dynamic performance
• Compatible with ADC12D1000/1600/1800 pins
• Low power consumption, further reduced at lower Fs
• Internally terminated, buffered, differential analog inputs
• R/W SPI interface extended control mode
• In dual-edge sampling mode, I and the Q-channel sample input the sampling clock rate twice
• Test the debug output mode of the system
• 15-bit programmable gain and 12-bit plus-sign offset
• Programmable T AD adjustment function
• 1:1 non-demuxed or 1:2 demuxed of LVDS output
• Multi-chip system with automatic synchronization function
• 1.9V ± 0.1V single power supply
• 292-ball BGA package (27mm x 27mm gauge x 1.27mm ball spacing 2.4mm) with no hot sink required

illustrate

The ADC10D1000/1500 is the latest advancement in the nationwide ultra-high-speed ADC series. This low-power, high-performance CMOS analog-to-digital converter delivers sample rates of up to 1.0/1.5 GSPS (non-DES mode) for dual-channel digitized signals, or up to 2.0/10-bit resolution 3.0 GSPS (DES mode) for a single channel. The ADC10D1000/1500 achieves excellent accuracy and dynamic performance while consuming less than 2.8/3.6 watts. Beyond the rated industrial temperature range, the product is packaged in a leaded or lead-free 292-ball thermally enhanced BGA package -40 ° C〜 to +85 ° C.

After the ADC10D1000/1500 is established, the 8-bit ADC GHz home features, architecture and capabilities. The expanded feature set includes multi-chip synchronization auto-sync, 15th place Programmable gain and 12-bit plus, programmable offset adjustment per channel. Improved internal tracking and holding amplifiers and extended self-calibration plans enable a very flat response to all dynamic parameters except Nyquist, producing a 100 MHz input signal and 1.0/1.5 9.1/9.0 significant bits (ENOB) while providing a 10 GHz sample rate -18 The bit error rate (CER), 1.0/1.5 dissipation from a single 1.9V supply GSPS in a typical 2.77/3.59 watt non-demultiplexing mode, this device is guaranteed to be code-free over the entire operating temperature range.

Each channel has its own independent DDR data clock, DCLKI and DCLKQ, and in the second phase, both channels are powered on, so there is only one data clock available for all the data captured, sending the sample clock as input at the same speed. If the 1:2 Demux mode is selected, the second 10-bit LVDS bus becomes active for each channel, and the output data rate is sent out twice slower, relaxing the data acquisition timing requirements. Sections can also be used as a single 2.0/3.0 GSPS ADC sampling I or Q input. The output format can be programmed to offset binary or two's complement and low-voltage differential signal transmission (LVDS) digital outputs are compatible with IEEE 1596.3-1996 adjustable common-mode voltage anomalies of 0.8V and 1.2V to allow power reduction to be controlled back to the aircraft.

Key specifications:

(Non-DES mode for non-Demux, FS = 1.0/1.5 GSPS, FIN = 100 MHz)

• Conversion rate

• power consumption

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• Broadband communication
• Data acquisition system
• Digital oscilloscope