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ADC10DL065CIVS
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ADC10DL065CIVS

  • 所属类别:ADC模数转换器
  • 产品名称:双路,10位,65 MSPS,3.3V,370mW A / D转换
  • 厂商:NSC
  • 生产批号:10+
  • 封装:TEPBGA
  • 库存状态:有库存
  • 库存量:20000
  • 最低订购量:1
  • 详细资料:点击查找ADC10DL065CIVS的pdf资料
  • 点击询价
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  • Product Introduction

peculiarity

  • +3.3 V single supply operation
  • Internal sampling and holding
  • Internal reference
  • The output is compatible with 2.4V to 3.6V
  • Power-down mode
  • Duty cycle stabilizer
  • Multiplexing output mode

illustrate

ADC10DL065 is a dual-channel, low-power monolithic CMOS analog-to-digital converter capable of up to 65 per second (MSPS) when converting analog input signals to 10 digits. The converter uses a differential pipeline architecture with digital error correction and an on-chip sampling and hold circuit to reduce power consumption while providing excellent power performance and a full power bandwidth of 250 MHz. Operating from a single +3.3 V supply, it reaches 9.8 effective bits at Nyquist ADC10DL065 and at 65 MSPS, including reference current consumption of only 370 mW. The power supply is cut off, reducing power consumption by 36 milliwatts.

Differential inputs provide a full-scale differential input swing equal to 2 times the V-band with the possibility of a single-ended input. It is recommended to make full use of differential inputs for optimal performance. The digital output from the two ADCs is available on a single-multiplexed 10-bit bus, or on different buses. Duty cycle stabilization and output data format can optionally use a four-state function pin. The output data can be set to offset binary or complement of two.

To mitigate the low voltage system of the interface, the ADC10DL065 of the digital output driver power pin can be connected to a separate analog supply voltage with a range of 2.4V. The device is available in a 64-pin TQFP package and will operate in industrial temperatures from -40°C to +85°C. Evaluation boards to ease the evaluation process.

Key specifications:

resolution

10th place

DNL

± 0.16 LSB (typical)

Signal-to-noise ratio (= 10 MHz f)

61 dB (typical)

SFDR (= 10 MHz f)

85 dB (typical)

Data delay

7 clock cycles

power consumption

 

-Job

370 mW (typical)

- Power-down mode

36 mW (typical)


apply

  • Ultrasound and imaging
  • instrumentation
  • Communication receiver
  • Sonar/radar
  • xDSL
  • DSP pre-end

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