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ADC10DL065CIVS
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ADC10DL065CIVS

  • Category:ADC analog-to-digital converter
  • Product Name:Dual, 10-bit, 65 MSPS, 3.3V, 370mW A/D conversion
  • Manufacturers:NSC
  • Production Batch Number:10+
  • Encapsulation:TEPBGA
  • Stock Status:There is stock
  • Stock Quantity:20000
  • Minimum order quantity: 1
  • Details:Click here to find pdf documentation for the ADC10DL065CIVS
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  • Product introduction

peculiarity

  • Operates from a single +3.3 V supply
  • Internal sampling and holding
  • Internal reference
  • The output is compatible from 2.4V to 3.6V
  • Power-down mode
  • Duty cycle stabilizer
  • Reuse output mode

illustrate

The ADC10DL065 is a dual, low-power monolithic CMOS analog-to-digital converter with the ability to convert analog input signals to 10-bit numbers up to 65 (MSPS) per second. The converter uses digital error correction and a differential pipeline architecture with on-chip sample-and-hold circuitry to reduce power consumption while providing excellent power performance and a full 250 MHz power bandwidth. Operating from a single +3.3 V supply, the Nyquist ADC10DL065 achieves 9.8 significant bits and consumes only 370 milliwatts at 65 MSPS, including the reference current. Disconnect the power supply and reduce power consumption by 36 milliwatts.

The differential input provides a full-scale differential input swing equal to 2x V with a single-ended inputtargetPossibility real estate. It is recommended to take full advantage of differential inputs for optimal performance. The digital outputs from both ADCs can be singleplexed on a 10-bit bus, or on a different bus. Duty cycle stabilization and output data format optionally use a four-state function pin. The output data can be set to offset binary or complement by two.

To mitigate the interface's low voltage system, the ADC10DL065 of the digital output driver supply pin can be connected to a separate analog supply voltage with a supply voltage range of 2.4V. This device is available in a 64-pin TQFP package and will be in the industrial temperature range of -40°C to +85°C. Evaluation board to ease the evaluation process.

Main specifications

resolution

10 bits

DNL

± 0.16 LSB (typical)

Signal-to-noise ratio (= f of 10 MHz)

61 dB (typical)

SFDR (= f at 10 MHz)

85 dB (typical)

Data latency

7 clock cycles

power consumption

 

-Job

370 mW (typical)

- Power-down mode

36 mW (typical)


apply

  • Ultrasound and imaging
  • Instrumentation
  • Communication receiver
  • Sonar / radar
  • xDSL
  • The front end of the DSP

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