ADC10DV200CISQE

• Product Introduction

 peculiarity   Operates from a single 1.8V supply. Power adjusts clock frequency. Internal sampling and holding. Internal or external references. Power-down mode. offset binary or 2 complement output data format. LVDS or CMOS output signal. 60-Pin LLP Package (9x9x0.8mm, 0.5-pin pitch) Clock duty cycle stabilizer. If the sampling bandwidth > 900MHz.   illustrate “  ADC10DV200 is a monolithic analog-to-digital converter capable of up to 200 megabytes per second (MSPS) when two analog input signals are converted into 10 digits. The digital output mode is optional and can be differential LVDS or CMOS signals. The converter uses a differential pipeline architecture with digital error correction and on-chip sampling and hold circuitry to minimize dead volume and power consumption while delivering excellent power performance. A unique sampling and holding stage that produces a full power bandwidth of 900MHz. Manufactured in the core CMOS process,  ADC10DV200 may operate from a single 1.8V supply. “  ADC10DV200 reaches approximately 9.6 effective bits and consumes 200 MSPS in LVDS mode, 170 MSPS in CMOS mode and 280 mW at 450 MW in Nyquist. By reducing the sampling rate, power consumption can be further reduced. Key specifications: resolution 10th place Conversion rate 200 MSPS ENOB 9.6 bits (typical) @翅 = 70MHz signal-to-noise ratio 59.9 dBFS (typical) @翅 = 70MHz SINAD 59.9 dBFS (typical) @翅 = 70MHz Spurious-free dynamic range (SFDR) (typical) of 82 dBFS @翅 = 70MHz LVDS power supply 450MW (typical) @ FS = 200MSPS CMOS power supply 280mW (typical) @ FS = 170MSPS Operating temperature. range -40°C to +85°C.

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