ADC12C105CISQ

• Full power bandwidth of 1 GHz
• Internal reference and sample-and-hold circuitry
• Low power consumption
• Data-ready output clock
• Clock duty cycle stabilizer
• Operates from a single +3.0 V or +3.3 V supply
• Power-down mode
• 32-pin LLP package (5x5x0.8mm, 0.5-pin pitch)

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The ADC12C105 is a high performance CMOS analog-to-digital converter capable of converting 12-bit digital signals with analog input rates up to 105 megasamples per second (MSPS). The converter uses a differential pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power dissipation and external component count while providing excellent dynamic performance. A unique sample-and-hold stage yielding a full power bandwidth of 1 GHz. The ADC12C105 may operate from a single +3.0 V or +3.3 V supply and consume low power.

A separate +2.5 V power supply for digital output interface reduces noise and low power operation. The power-down feature reduces power consumption at very low levels, while also allowing fast wake-up times to operate fully. The differential input accepts a 2V full-scale differential input swing. A regulated 1.2V internal reference voltage is provided, or the ADC12C105 can operate with an external 1.2V reference. The pin-selectable output data format (offset to 2's complement binary) and duty cycle are stable. The duty cycle stability maintains broad performance over a clock duty cycle.

The ADC12C105 is available in a 32-lead LLP package and operates over the industrial temperature range of -40°C to +85°C

Main specifications

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