ADC12DC080CISQE

• Internal sample-and-hold circuitry and precision reference
• Low power consumption
• Clock duty cycle stabilizer
• Operates from a single 3.0 V supply
• Power-down mode
• Offset binary or 2 complement output data format
• 60-pin LLP package (9x9x0.8mm, 0.5-pin pitch)

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The ADC12DC080 is a high performance CMOS analog-to-digital converter capable of converting two analog input signals to 12-bit numbers at up to 80 megasamples per second (MSPS). These converters feature a differential pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power dissipation and external component count while providing excellent dynamic performance. A unique sample-and-hold stage yielding a full power bandwidth of 1 GHz. The ADC12DC080 may operate from a single +3.0 V supply. The power-down feature reduces power consumption at very low levels, while also allowing fast wake-up times to operate fully. The differential input provides a 2V full-scale differential input swing. A regulated 1.2V internal reference voltage is provided, or the ADC12DC080 can be operated with an external 1.2V reference. The pin-selectable output data format (offset to 2's complement binary) and duty cycle are stable. The duty cycle stability maintains broad performance over a clock duty cycle.

The ADC12DC080 is available in a 60-lead LLP package and operates over the industrial temperature range of -40°C to +85°C

Main specifications

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• High IF sampling receiver
• Wireless base station receiver
• Test and measurement equipment
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• Portable meter