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ADC12QS065CISQ
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ADC12QS065CISQ

  • Category:ADC analog-to-digital converter
  • Product Name:Four 12-bit 65 MSPS A/D converters
  • Manufacturers:NSC
  • Production Batch Number:10+
  • Encapsulation:TEPBGA
  • Stock Status:There is stock
  • Stock Quantity:20000
  • Minimum order quantity: 1
  • Details:Click here to find pdf documentation for the ADC12QS065CISQ
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  • Product introduction

peculiarity

  • Operates from a single +3.3 V supply
  • Internal sample-and-hold circuit and internal reference
  • Low power consumption
  • Power-down mode
  • Clock and data frame timing
  • 780 Mbps serial LVDS data rate (clocked at 65 MHz)
  • The LVDS serial output is rated for 100 ohms

illustrate

The ADC12QS065 is a low power, high performance CMOS 4-channel analog-to-digital converter with serialized LVDS outputs. The ADC12QS065 digitizes the signal bits to 12-bit resolution and samples at rates up to 65 MSPS while consuming only 200 milliwatts from a typical 3.3V single-supply supply/ADC. The sampled data is converted into a high-speed data stream with serial LVDS output. LVDS dual auxiliary data acquisition of clocks and frames. The ADC12QS065's six differential pairs transfer data on the backplane or cable, also making PCB design easier. In addition, reducing the number of cables, PCB traces and connector size greatly reduces costs.

No missing codes are guaranteed over the full operating temperature range. The pipeline ADC architecture implements 11 significant bits at 65 MSPS across the entire Nyquist band.

When not converted, the power dissipation can be reduced to the pull PD (low power) pin to a high level, and the typical power consumption when put into a low-power state is less than 3 megawatts, from which the converter recovers less than 5 milliseconds. The ADC12QS065's speed, resolution, and single-supply operation make it ideal for ultrasound, imaging, video, and a variety of communications applications. Over the industrial (-40°C to +85°C) temperature range, the ADC12QS065 is available in a 60-lead LLP with exposed pads (9x9x0.8mm with 0.5mm pin pitch) in a 60-pin LLP package.

Focus on specifications

resolution

12 bits

DNL

± 0.3 LSB (typical)

Signal-to-noise ratio (fat= 5 MHz)

69 dB (typical)

of SFDR(fat= 5 MHz)

83 dB (typical)

Effective number of digits (at Nyquist frequency)

11 bits (typical)

power consumption

 

- Operation, 65 MSPS, per ADC

200 mW (typical)

- Power-down mode


apply

  • ultrasonic
  • Medical imaging
  • communication
  • Portable meter
  • Digital video

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