ADC14155CISQ

• Full power bandwidth of 1.1 GHz
• Internal sample-and-hold circuitry
• Low power consumption
• Internal precision 1.0V reference
• Single-ended or differential clocking mode
• Data-ready output clock
• Clock duty cycle stabilizer
• Dual +3.3 V and +1.8 V supplies (+/- 10%)
• Power-down mode
• Offset binary or two's complement output data format
• 48-Pin LLP Package (7x7x0.8mm, 0.5mm Pin Spacing)

illustrate

The ADC14155 is a high performance CMOS analog-to-digital converter capable of converting 14-bit digital-to-analog input signals to large samples up to 155 per second (MSPS). The converter uses differential, pipelined digital error correction and an on-chip sample-and-hold circuit to reduce power consumption and external component count architectures while providing excellent dynamic performance. A unique sample-and-hold stage yields a full power bandwidth of 1.1 GHz. The ADC14155 operates from dual +3.3 V and +1.8 V supplies and consumes 967 mW of 155 MSPS.

The independent +1.8 V digital output interface power supply allows low-power operation with reduced noise. The power-down feature reduces power consumption to 5 milliwatts of input clock disability, while also allowing fast wake-up times to be fully operational.

The differential input provides a fully differential input swing equal to 2x the reference voltage. A regulated 1.0V internal reference voltage is provided, or the ADC14155 can be operated with an external reference.

The ADC14155 can be configured for single-ended or differential operation. The clock mode (differential vs. single-ended) and output data format (complement of offset binary ratio 2) are pin-selectable. A duty cycle stability maintains performance over a wide clock duty cycle range.

The ADC14155 is available in a 48-pin LLP package and operates over the -40°C industrial temperature range to +85°C

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