ADC14DC080CISQ

• Internal sample-and-hold circuitry and precision reference
• Low power consumption
• Clock duty cycle stabilizer
• Operates from a single +3.0 V supply
• Power-down mode
• Offset binary or two's complement output data format
• 60-pin LLP package (9x9x0.8mm, 0.5mm pin pitch)

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The ADC12DC080 is a high performance CMOS analog-to-digital converter with the ability to convert two analog input signals into 12-bit words to large samples of up to 80 per second (MSPS). These converters feature differential pipelined digital error correction and an on-chip sample-and-hold circuit to reduce power consumption and external component count architectures while providing excellent dynamic performance. A unique sample-and-hold phase yields a full power bandwidth of 1 GHz. The ADC12DC080 can operate from a single +3.0 V supply. The power-down feature reduces power consumption at very low levels while still allowing fast wake-up times for full operation. The differential input provides a 2V full-scale differential input swing. A regulated 1.2V internal reference voltage is provided, or the ADC12DC080 can be operated with an external 1.2V reference. The output data format (complement binary with offset ratio 2) and duty cycle stabilizer are pin-selectable. Duty cycle stability maintains performance over a wide clock duty cycle range.

The ADC12DC080 is available in a 60-pin LLP package and operates over the -40°C industrial temperature range to +85°C

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