ADC14DS105CISQE

• Internal sampling hold circuitry and precision reference
• Low power consumption
• Clock duty cycle stabilizer
• Single +3.0 V supply operation
• Power-down mode
• offset binary or two-complement output data format
• 60-Pin LLP Package (9x9x0.8mm, 0.5mm Pin Pitch)

illustrate

The ADC12DC080 is a high-performance CMOS analog-to-digital converter with a conversion rate of two analog input signals into 12-bit words and the ability to convert large samples up to 80 per second (MSPS). These converters employ differential pipeline digital error correction and an on-chip sampling and hold circuitry to reduce power consumption and external component count architecture while providing excellent dynamic performance. A unique sample and hold stage yields a full power bandwidth of 1 GHz. The ADC12DC080 can work from a single +3.0 V supply. The power-down feature reduces power consumption at very low levels while still allowing for a quick wake-up time for full operation. The differential input provides a 2V full-scale differential input swing. A stable 1.2V internal reference voltage is supplied, or ADC12DC080 can be operated with an external 1.2V reference. The output data format (complement binary with offset ratio 2) and duty cycle stabilizer are selectable by pin. The duty cycle is consistently maintained over a wide range of clock duty cycle performance.

The ADC12DC080 is available in a 60-pin LLP package and operates from a -40°C industrial temperature range to +85°C

Key norms

apply

• High IF sampling receiver
• Wireless base station receiver
• Test & Measurement Equipment
• Communication instruments
• Portable instrumentation