ADC16DV160CILQ
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ADC16DV160CILQ

  • Category:converter
  • Product Name:Channel, 16-bit, 160 MSPS analog-to-digital converter
  • Manufacturers:NSC
  • Production Batch Number:11+
  • Encapsulation:QFN
  • Stock Status:There is stock
  • Stock Quantity:2000
  • Minimum order quantity: 1
  • Details:Click here to find pdf information on the ADC16DV160CILQ
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  • Product introduction

peculiarity

  • Low power consumption
  • Precision reference and sample-and-hold circuitry on the chip
  • The chip is automatically calibrated at power-up
  • Dual data rate LVDS output ports
  • Dual-supply operation: 1.8V and 3.0V operation
  • Optional input ranges: 2.4 and 2.0 VPP
  • Flip the sampling edge with clock divider consisting of 2 options
  • 1 or 2 internal clock divideovers
  • On-chip low jitter duty cycle stabilizer
  • Power-down mode and sleep mode
  • Output fixed pattern generation
  • Output clock position adjustment
  • 3-wire SPI
  • Offset binary or 2 complement data format
  • 68-pin LLP package (10x10x0.8, 0.5 pin pitch)

illustrate

The ADC16DV160 is a monolithic dual-channel, high-performance CMOS analog-to-digital converter capable of converting 16-bit digital signals with analog input rates up to 160 megasamples per second (MSPS). The converter uses digital error correction and an on-chip sample-and-hold differential pipeline architecture to minimize power dissipation and external component count while providing excellent dynamic performance. Automatic power calibration allows for excellent power performance with reduced variation in some sections, and the ADC16DV160 can be recalibrated at any time via a 3-wire serial peripheral interface (SPI). The integration of low noise and stable reference voltage and differential reference buffer amplifiers simplifies board-level design. The cycle stabilizer with very low on-chip responsibility and cumulative jitter is a wide range of input clock duty cycles without compromising power performance. A unique sample-and-hold stage yields a full power bandwidth of 1.4 GHz. The interface between the ADC16DV160 and a receiver can be easily verified and optimized through fixed patterns for generating and outputting clock position functions. Digital data is available via dual data rate LVDS outputs - 68-pin, 10mm × 10mm LLP packages. The ADC16DV160 operates dual-supply +1.8 V and +3.0 V with power-down capability to reduce power consumption at very low levels while allowing a quick return to full operation.

Main specifications

resolution

16 bits

Conversion rate

160 MSPS

Signal-to-noise ratio

(@F = 30 MHz)

(@F = 197 MHz)

78 dBFS (typical)

76 dBFS (typical)

Spurious-free dynamic range (SFDR)

(@F = 30 MHz)

(@F = 197 MHz)

95 dBFS (typical)

89 dBFS (typical)

Full power bandwidth

1.4 GHz (typical)

power consumption

The core of each channel

- LVDS drives

-total

612 mW (typical)

117 mW (typical)

1.3W (typical)

Operating temperature range

-40 ° C〜85 ° C


apply

  • Multi-carrier, multi-standard base station receiver

  • - MC-GSM/EDGE, CDMA2000, UMTS, LTE and WiMAX
  • High IF sampling receiver
  • Diversity channel receiver
  • Test and measurement equipment
  • Communication instruments
  • Portable meter

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