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ADC16DV160CILQE
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ADC16DV160CILQE

  • 所属类别:转换器
  • 产品名称:双通道,16位,160 MSPS模拟数字转换器
  • 厂商:NSC
  • 生产批号:10+
  • 封装:QFN68
  • 库存状态:有库存
  • 库存量:20000
  • 最低订购量:1
  • 详细资料:点击查找ADC16DV160CILQE的pdf资料
  • 点击询价
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  • Product Introduction

peculiarity

  • Low power consumption
  • Precision reference and sampling and holding circuitry in chips
  • The upper chip is automatically calibrated when powered on
  • Dual data rate LVDS output ports
  • Dual Supply Operation: 1.8V and 3.0V operation
  • Selectable input ranges: 2.4 and 2.0 V PP
  • Flip the sample edge with clock crossover by 2 options
  • 1 or 2 internal clock crossovers
  • On-chip low jitter duty cycle stabilizer
  • Power Loss Mode and Sleep Mode
  • Output fixed pattern generation
  • Output clock position adjustment
  • 3-wire SPI
  • offset binary or 2 complement data format
  • 68-Pin LLP Package (10x10x0.8, 0.5 Pin Pitch)

illustrate

ADC16DV160 is a monolithic dual-channel, high-performance CMOS analog-to-digital converter capable of converting 16-bit voice signals with an analog input rate of up to 160 megaseconds per second (MSPS). The converter uses digital error correction and a differential pipeline architecture for on-chip sampling and holding circuitry to minimize power consumption and the number of external components while providing excellent dynamic performance. Automatic power calibration allows for excellent power performance and reduced variation in some sections, as well as ADC16DV160 can be recalibrated at any time via a 3-wire serial peripheral interface (SPI). Integrated low-noise and stable reference voltage and differential reference buffer amplifiers simplify board-level design. The cycle stabilizer with extremely low on-chip responsibility and cumulative jitter does not affect power performance, and a wide range of input clock duty cycles. A unique sampling and hold stage that produces a full power bandwidth of 1.4 GHz. The interface between the ADC16DV160 and a receiver can be easily verified and optimized through the generation of fixed patterns and the position function of the output clock. The digital data is provided by providing dual data rate LVDS outputs – 68 pins, 10 mm × 10 mm LLP packages. ADC16DV160 operates dual +1.8 V and +3.0 V power-down capabilities to reduce power consumption at very low levels while allowing for a quick return to full operation.

Key specifications:

resolution

16th place

Conversion rate

160 MSPS

signal-to-noise ratio

(@F = 30 MHz)

(@F = 197 MHz)

78 dBFS (typical)

76 dBFS (typical)

Spurious-free dynamic range (SFDR)

(@F = 30 MHz)

(@F = 197 MHz)

95 dBFS (typical)

89 dBFS (typical)

Full power bandwidth

1.4 GHz (typical)

power consumption

The core of each channel

- LVDS drivers

-total

612 milliwatts (typical)

117 milliwatts (typical)

1.3W (typical)

Operating temperature range

-40 ° C〜85 ° C


apply

  • Multi-carrier, multi-standard base station receiver

  • •MC-GSM/EDGE, CDMA2000, UMTS, LTE and WiMAX
  • High IF sampling receiver
  • Diversity channel receiver
  • Test & Measurement Equipment
  • Communication instruments
  • Portable instrumentation

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