ADC16V130CISQ

• Dual Supplies: 1.8V and 3.0V Operation
• When the chip automatically calibrates the electricity
• Low power consumption
• Multi-level multi-pin clock/DF and Parkinson's disease
• Power-down and sleep modes
• Accurate reference and sample-and-hold circuitry on the chip
• On-chip low jitter duty cycle stabilizer
• Offset binary or two's complement data format
• Full data rate LVDS output port
• 64-pin LLP package (0.5mm pitch for 9x9x0.8)

illustrate

The ADC16V130 is a monolithic high-performance CMOS analog-to-digital converter capable of converting large samples at 16-bit digital-to-analog input signals at rates up to 130 per second (MSPS). The converter uses differential, pipelined digital error correction and an on-chip sample-and-hold circuit architecture to minimize power consumption and external component count while providing excellent dynamic performance. Automatic electrical calibration enables excellent power performance and reduced part-to-part variation, while the ADC16V130 can be recalibrated at any time by declaring and then claiming a power loss. Integrated low noise and stable voltage reference and differential reference buffer amplifier EASIES board level design. The power performance of the on-chip low-tax additional jitter cycle stabilizer does not affect the input clock cycles over its wide range of responsibilities. A unique sample-and-hold phase yields a full power bandwidth of 1.4 GHz. Digital data is made possible by providing full data rate LVDS outputs - 64-pin, 9mm x 9mm LLP packages. The ADC16V130 dual-supply operation provides a power-saving feature to reduce very low levels of power consumption while allowing a quick return to full operation of +1.8 V and +3.0 V.

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• High IF sampling receiver
• Multicarrier base station receiver

• GSM/EDGE networks, CDMA2000, UMTS LTE and WiMAX
• Test and measurement equipment
• Communication instruments
• Data acquisition
• Portable meter