ADC16V130CISQ

• Dual Supply: 1.8V and 3.0V operation
• When the chip automatically calibrates the electricity
• Low power consumption
• Multi-level multi-function pin clock/DF and Parkinson's disease
• Power loss and sleep mode
• Accurate reference and sampling hold circuitry on the chip
• On-chip low jitter duty cycle stabilizer
• offset binary or complement data format
• Full data rate LVDS output port
• 64-Pin LLP Package (9x9x0.8 with 0.5mm Pin Pitch)

illustrate

The ADC16V130 is the ability of a monolithic high-performance CMOS analog-to-digital converter to convert large samples at speeds up to 130 per second (MSPS) into a 16-bit digital-analog input signal. The converter uses differential, pipeline-digital error correction, and an on-chip sampling and hold circuit architecture to minimize power consumption and the number of external components while providing excellent dynamic performance. Automatic electrical calibration provides excellent power performance and reduced part-to-part variation, while ADC16V130 can be recalibrated at any time by declaring and then claiming a power off. Integrated low-noise and stable voltage reference and differential reference buffer amplifier easies board-level design. The on-chip low-tax additional jitter period stabilizer's dynamic performance does not affect the input clock cycle over its wide range of responsibilities. A unique sampling and holding stage produces a full power bandwidth of 1.4 GHz. The digital data is made possible by providing a full data-rate LVDS output - a 64-pin, 9mm x 9mm LLP package. The ADC16V130 dual-supply operation provides power savings to reduce very low levels of power consumption while allowing for a quick return to full operation +1.8 V and +3.0 five.

Key norms

apply

• High IF sampling receiver
• Multi-carrier base station receiver

• In GSM/EDGE networks, LTE and WiMAX for CDMA2000, UMTS
• Test & Measurement Equipment
• Communication instruments
• Data acquisition
• Portable instrumentation