ADN4670是一款低压差分信号(LVDS)
Clock driver,可以将一路差分时钟输入信号扩展为十路差分时钟输出。这款器件可以通过简单的串行接口进行编程,以便选择两路时钟输入之一(CLK0/
CLK0 或CLK1/
CLK1) ,以及使能或禁用(三态)任何一路差分输出(Q0/
Q0至Q9/
Q9) 。ADN4670设计用于50 Ω传输线路环境。
When the enable input EN is high, the device can be programmed by entering 11 data bits into the shift register. The first 10 bits determine which outputs are enabled (0 = disabled, 1 = enable) and the 11th bit selects the clock inputs (0 = CLK0, 1 = CLK1). The 12th clock pulse transmits data from the shift register to the control register.
The ADN4670 is rated for an industrial temperature range and is available in a 32-pin LFCSP package.
应用
时钟分配网络