ADP7105是一款CMOS、低压差(LDO)
Linear regulator，采用3.3 V至20 V电源供电，最大输出电流为500 mA。这款高输入电压LDO适用于调节1.22 V至19 V供电的高性能模拟和混合信号电路。该器件采用先进的专有架构，提供高电源抑制、低噪声特性，仅需一个1 μF小型陶瓷输出电容，便可实现出色的线路与负载瞬态响应性能。
ADP7105 offers three fixed output voltage options and an adjustable output model that can be adjusted from 1.22 V to 19 V via an external feedback divider. ADP7105 can be connected to an external soft-start capacitor to program the start-up.
Note that in the datasheet, the detection function (SENSE) of the SENSE/ADJ pin is only for fixed output voltage mode, while the adjustable input function (ADJ) is only for adjustable output voltage mode. For example, Figure 1 shows the detection function and Figure 2 shows the adjustable input function.
ADP7105 output noise voltage is 15 μV rms and is not affected by the output voltage. These devices have a "power good" digital output pin that allows the power system monitor to check if the output voltage is normal. The user-programmable precision undervoltage latching feature allows for easy control of the timing of multiple power supplies.
ADP7105 available in 8-pin 3 mm × 3 mm LFCSP and 8-pin SOIC packages. LFCSP provides an ultra-compact solution with excellent thermal performance to meet the needs of applications with up to 500 mA output current in a small and low profile board space.
apply
-
适应噪声敏感应用：
ADC和DAC电路、精密放大器、
高频振荡器、时钟和PLL
-
通信和基础设施
-
医疗和保健
-
工业和仪器仪表