ADP7112 is a CMOS, low-dropout (LDO) linear regulator that operates from a 2.7 V to 20 V supply with a maximum output current of 200 mA. This high-input voltage LDO is suitable for high-performance analog and mixed-signal circuits that regulate 20 V to 1.2 V supply. The device uses an advanced proprietary architecture that provides high power rejection, low noise characteristics, and excellent line and load transient response performance with a single small 2.2 μF ceramic output capacitor. ADP7112 regulator output noise is 11 μVrms, independent of fixed option output voltages of 5 V and below.
ADP7112 offers 16 fixed output voltage options. These options are available in the following voltages: 1.2 V (adjustable), 1.8 V, 2.5 V, 3.3 V, and 5.0 V. Other voltages are available on special requirements: 1.5 V, 1.85 V, 2.0 V, 2.2 V, 2.75 V, 2.8 V, 2.85 V, 3.8 V, 4.2 V and 4.6 V.
Each fixed output voltage can be adjusted above the initial set point via an external feedback divider. This allows ADP7112 to deliver an output voltage of 1.2 V to VIN–VDO with high PSRR and low noise.
ADP7112 supports user-programmable soft-start via external capacitors. ADP7112 is available in 6-pin, 1 mm × 1.2mm WLCSP packages, making it very compact.
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适应噪声敏感应用
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ADC和DAC电路、精密放大器,适合为VCO Vtune控制供电
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通信和基础设施
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医疗和保健
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工业与仪器仪表