| Model |
Manufacturers |
lot number |
encapsulation |
illustrate |
| CD4099B |
TI |
10+ |
SOP |
CMOS 8-bit addressable latches |
| CD4076B-MIL |
TI |
10+ |
SOP |
CMOS 4-bit Class D registers with clock and three-state output |
| CD4076B |
TI |
10+ |
SOP |
CMOS 4-bit Class D registers with clock and three-state output |
| CD4044B-MIL |
TI |
10+ |
SOP |
CMOS quad and non-R/S latches with three-state outputs |
| CD4044B |
TI |
10+ |
SOP |
CMOS quad and non-R/S latches with three-state outputs |
| CD4043B-MIL |
TI |
10+ |
SOP |
CMOS quad or non-R/S latches with three-state outputs |
| CD4043B |
TI |
10+ |
SOP |
CMOS quad or non-R/S latches with three-state outputs |
| CD4042B-MIL |
TI |
10+ |
SOP |
CMOS quad clock "D" latches |
| CD4042B |
TI |
10+ |
SOP |
CMOS quad clock "D" latches |
| SN74S112A |
TI |
10+ |
SOP |
Dual J-K falling edge triggers with zero and presets |
| SN74LVC112A |
TI |
10+ |
SOP |
Dual falling edge J-K trigger with zero and presets |
| SN74LS73A |
TI |
10+ |
SOP |
Dual J-K trigger with clearing |
| SN74LS112A |
TI |
10+ |
SOP |
Dual J-K falling edge triggers with zero and presets |
| SN74LS109A |
TI |
10+ |
SOP |
Dual J-K rising edge triggers with zero and preset functions |
| SN74LS107A |
TI |
10+ |
SOP |
Dual J-K trigger with clearing |
| SN74HC112 |
TI |
10+ |
SOP |
Dual J-K falling edge triggers with zero and presets |
| SN74HC109 |
TI |
10+ |
SOP |
Dual J-K rising edge triggers with zero and preset functions |
| SN74F112 |
TI |
10+ |
SOP |
Dual J-K falling edge triggers with zero and presets |
| SN74F109 |
TI |
10+ |
SOP |
Dual J-K rising edge triggers with zero and preset functions |
| SN74AS109A |
TI |
10+ |
SOP |
Dual J-K rising edge triggers with zero and preset functions |