CDCE72010RGCT
illustrate
The CDCE72010 is a high-performance, low-phase noise and low-offset clock synchronizer that synchronizes a VCXO (Voltage-Gauge Crystal Oscillator) or VCO (Voltage-Gauge Oscillator) frequency with one of two reference clocks. The clock path is fully programmable, providing a high degree of flexibility for the user. The following relationships apply to separation:
Frequency (VCXO_IN or AUX_IN) / Frequency (PRI_REF or SEC_REF) = (P * north) / (R* male)
Clock operation up to 1.5GHz at VC(X) O_IN through external VC(X) O and loop filtering element selection. The PLL loop bandwidth and damping factor can be adjusted to meet different system requirements.
The lockable CDCE72010 is maintained in fail-safe and system redundancy mode with two reference clock inputs (PRI_REF and SEC_REF) and one supported frequency.
characteristic
High performance LVPECL, LVDS, LVCMOS PLL clock synchronization
Two reference clock inputs (primary and secondary school clocks) redundant with manual or automatic selection support
Accepts references up to 500MHz (or two LVCMOS inputs up to 250MHz) with two differential inputs (LVPECL or LVDS) as PLL references
VCXO_IN clock synced to one or two base clocks
VCXO_IN frequency up to 1.5GHz (LVPECL) for LVDS 800MHz and 250MHz signal levels LVCMOS channels
The output can be a combination of LVPECL, LVDS, and LVCMOS (up to 10 differential LVPECL or LVDS outputs or up to 20 LVCMOS outputs), and output 9 can be converted to a second venture (X) with one auxiliary input
The crossover outputs can be optionally divided by 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 18, 20, 24, 28, 30, 32, 36, 40, 42, 48, 50, 56, 60, 64, 70 or 80 in each output individually up to eight dividers. (Except for outputs 0 and 9 0 follow output 1 output crossover and output 9 follow output 8 crossover)
SPI controllable device settings
Individuals can output control through the SPI interface
Integrated on-chip non-volatile memory (EEPROM) to store settings without the need to apply to high-voltage devices
Optional configuration pins to select two default settings stored in EEPROM
Efficient and low jitter PLL loop bandwidth from cleaning
Very low phase noise at the core of the phase-locked loop
Programmable phase offset (reference input/output)
The wide charge pump current range from 200μA to 3mA
Dedicated charge pump power supply voltage range wide tuned VCO
The preset charge pump is set for the V CC_CP/2 fast center frequency of the VC(X) O-BUS OF SPI, via control
SERDES boot mode (depending on the scope of the VCXO)
Auxiliary Inputs: Output 9 can be used as a driver for a second VCXO, or as a PLL feedback signal
RESET or HOLD input pins as reset or hold functions